Statement of originality:
This original tutorial was created by Xinyi Electronic Technology (Shanghai) Co., Ltd. (ALINX), and the copyright belongs to the company. If you want to reprint, you need to authorize and indicate the source.
Applicable board models:
The experimental Vivado project directory is “ps_axi_gpio/vivado”.
The experimental vitis project directory is “ps_axi_gpio/vitis”.
Some people may ask, why are we talking about GPIO and LED lights again? I think it is too cumbersome, but GPIO is the basic operation of ZYNQ. This tutorial strives to share various methods with everyone, such as MIO and EMIO on the PS side, axi gpio on the PL side, Including the two directions of input and output, as well as the basic operations of PS and PL, so I still hope that everyone will learn patiently.
I mentioned earlier how to use the EMIO on the PS side to light up the LED on the PL side, but there is no interaction with the PL side. This chapter introduces another control method. AXI GPIO can be used in ZYNQ to control the LED light on the PL side through the AXI bus. At the same time, it also introduces the use of PL terminal buttons.
The biggest question when using zynq is how to combine PS and PL. In other SOC chips, there are GPIOs. This experiment uses an AXI GPIO IP core to let the PS side control the LED lights on the PL side through the AXI bus. Although the experiment Simple, but allows us to understand how PL and PS are combined.
1. Principle introduction
An AXI GPIO module has two GPIOs, GPIO and GPIO2, namely channel1 and channel2, which are bidirectional IO.
FPGA engineer job content
The following is the FPGA engineer responsible for the content.
2. Vivado project establishment
1) Open “ps_hello” and save it as a Vivado project named “ps_axi_gpio”, indicating that the PS controls gpio through the AXI bus
After “Create project subdirectory” is checked, a subdirectory will be created under the directory, and if “Include run results” is checked, the compiled results will be included
2) Double-click xx.bd to open block design
Add AXI GPIOs
3) Add an AXI GPIO IP core
4) Double-click the “axi_gpio_0” configuration parameter just added
5) Select “All Outputs”, because the LED is controlled here, as long as the output is enough, fill in “GPIO Width” 1, control 1 LED, and click OK. If you want to use channel2, you need to turn on “Enable Dual Channel”, which also enables GPIO2.
6) Click “Run Connection Automation” to complete part of the automatic connection
7) Select the port to be automatically connected, select all here, and click OK
8) Click “Optimize Routing” to optimize the layout. At the same time, you can see two more modules, one is the Processor System Reset module, which provides a reset signal for the same clock domain as a synchronous reset module. The AXI Interconnect module is an AXI bus interconnection module, which is used for cross-connection of AXI modules.
In this application, we can see that the HPM0_LPD port of ZYNQ is used. This interface is used to access PL-side data. In most applications, it is used to configure the registers of the PL-side module.
The reset signal is provided by the reset output of ZYNQ. It is best to add a reset module for each clock domain, which can be searched and added according to the name below the module.
9) Modify the name of the GPIO port
10) Change the name to leds
11) Add another AXI GPIO, connect the PL terminal button, configure GPIO parameters, all are input, width is 1, enable interrupt
12) Use autoconnect
13) Then change the port name to keys
14) Since it is an interrupt from the PL side, it is necessary to configure the interrupt of the ZYNQ processor here, and set IRQ0[0-7] to 1
15) Connect ip2intc_irpt to pl_ps_irq
16) Save the design, click xx.bd, right click Generate Output Products
17) In the generated Verilog file, you can see that there are “leds_tri_o” and “keys_tri_i” ports, and you need to assign pins to them. When binding pins, the pin names in this file shall prevail.
3. The XDC file constrains the PL pins
1) Create a new xdc constraints file
2) The file name is led
3) Add content to led.xdc, the port name must be consistent with the top-level file port
4) Generate bit file
5) Export hardware FileExportExport Hardware
6) Because PL is used, select “Include bitstream” and click “OK”
Software Engineer Job Content
The following is the responsibility of software engineers.
4. Vitis programming
4.1 AXI GPIO lights up the LED at the PL end
1) Create a platform. For the creation process, refer to the chapter “PS RTC Interrupt Experiment”
2) Facing an unfamiliar AXI GPIO, how do we control it? We can try the routines that come with Vitis
3) Double-click “system.mss”, find “axi_gpio_0”, here you can click “Documentation” to view related documents, here is no demonstration, click “Import Examples”
4) There are multiple routines in the pop-up dialog box, you can guess from the name, here choose the first “xgpio_example”
5) It can be seen that the routine is relatively simple, with just a few lines of code, the operation of AXI GPIO is completed
Many GPIO-related API functions are used in it. You can learn more about it through the documentation. You can also select the function and press “F3” to view the specific definition. If you still can’t understand how to use AXI GPIO with this information, it means that you need to supplement the basics of C language.
In fact, these functions are all operating GPIO registers. There are not many AXI GPIO registers, mainly the data registers GPIO_DATA and GPIO2_DATA of the two channels, the direction control of the two channels GPIO_TRI and GPIO2_TRI, and the global interrupt enable register GIER, IP The interrupt enable IP IER and the interrupt status register ISR, the specific function can be seen in the document pg144 of AXI GPIO.
For example, when entering the function of setting the direction of GPIO, you can see that you are writing data to the GPIO_TRI register of GPIO to control the direction.
Other functions can also be studied by themselves according to this method.
4.2 Download and debug
First compile the APP project, the previous routine of the compilation method has been introduced. Although Vitis can provide some routines, some routines need to be modified by yourself. This simple LED routine will not be modified. Try to run it, and find that it cannot achieve the expected effect, and even prompts some errors. After downloading, you can see that LED1 of the development board flashes quickly.
4.3 Realization in register mode
If you feel that the API functions provided by Xilinx are cumbersome and inefficient, you can also control the LED by operating registers.
For example, we create a new axi_led project below, and modify helloworld.c as follows.
The base address GPIO_BASEADDR defined in it can be found in xx.xsa
Since we only enabled channel1, the following register addresses are defined
In this way, the method of directly operating registers will be more efficient than calling Xilinx API functions, and it is more intuitive, which is very helpful for understanding how the program runs. But for large projects, this method is more complicated to use, and the choice is mainly based on personal needs.
4.4 AXI GPIO PL terminal key interrupt
The interrupt in the previous timer interrupt experiment belongs to the internal interrupt of PS. The interrupt in this experiment comes from PL. PS can receive up to 16 interrupt signals from PL, all of which are triggered by rising edge or high level.
1) Same as the previous tutorial, if we are not familiar with Vitis programming, we try to use Vitis’s own routines to modify, select “xgpio_intr_tapp_example”
2) Part of the code needs to be modified. The axi gpio module of the button is called axi_gpio_1, and its device id can be found in xparameters.h
3) Then you can modify the macro definition of GPIO and interrupt number as follows
4) Modify the test delay time, so that we have enough time to press the button
4.5 Download and debug
Save the file, compile the project, open the serial port terminal, and download the program. If the key is not pressed, the serial port will display “No button pressed.” If the “KEY1” key is pressed, it will display “Successfully ran Gpio Interrupt Tapp Example”.
5. Experiment summary
Through experiments, we learned that PS can control PL through AXI bus, but it hardly reflects the advantages of ZYNQ, because controlling LED lights, whether it is ARM or FPGA, can be easily completed, but if the LED is replaced by a serial port, the control of 100 I don’t think there is any SOC that can complete this function, but only ZYNQ can. This is the difference between ZYNQ and ordinary SOC.
The PL terminal can send an interrupt signal to the PS, which improves the efficiency of data interaction between the PL and the PS, and interrupt processing is required in applications that require a large number and low latency.
By the end of this chapter, we have finished explaining how to use ZYNQ’s PS-side MIO, EMIO, and PL-side GPIO, including input, output, and interrupt processing. These are the most basic operations. You still need to think more and understand clearly.
6. Knowledge sharing
1) After the design is completed, you can see that in the Address Editor, the address space has been allocated for the AXI peripheral, and the offset address and space size can be modified.
However, there are restrictions on modifying the offset address. For details, refer to the chapter System Address of the UG1085 document. The AXI peripheral is connected to the M_AXI_HPM0_LPD port, and it is modified in the address space from 8000_0000 to 9FFF_FFFF.
2) When using a module, supporting documents are needed to assist development, but how to find these documents, such as the IP of XILINX, open the configuration of the module, click Documentation in the upper left corner, and then click Product Guide, if you are installing Vivado When DocNav is installed, it will jump to open the document.
This function requires a computer to be connected to the Internet, and DocNav will load documents from the website. You can click the download button to download to the local.
Another method is to search for data downloads on the Xilinx official website according to the name of the module (the page may change)