Amd launched the 7Nm zen2 architecture this year. At present, in addition to APU and notebook versions, it has been fully upgraded in desktop and server versions. The next generation is the zen3 architecture, which will use the 7Nm EUV process. At present, the architecture design has been completed.

Compared with the current zen2 architecture, what has zen3 architecture changed? At present, there is no official clear statement. Reliable sources say that the IPC performance of zen3 architecture will be improved by 8%, and the core frequency will be increased by about 200MHz, even if it is no more than 5GHz, it is infinitely close.

Zen3 architecture or further increase the capacity of L3 cache by 50-100% over the current zen2

Zen2 processor has realized the design of desktop with a maximum of 16 cores and 32 threads. It is expected that the number of cores of zen3 processor will not change, and the cache architecture will be the focus of improvement. Before that, amd officially said that unlike zen2, each group of CCX shares 16MB of three buffers, and zen3 provides 32MB of three buffers for the whole core.

However, according to the latest disclosure, AMD will not only change the structure of L3 cache, but also further increase the capacity of L3 cache to 48MB or 64MB, 50-100% higher than the current zen2.

Adding L3 cache helps to solve the problem of delay in the design of AMD’s CCX architecture, so that more data can be stored in L3 cache, reducing the call to DRAM memory. After all, the natural delay of separated IO core is higher than that of native core, and AMD can only use this way to reduce the delay as much as possible.

Of course, the premise that AMD can increase L3 cache by half or half is also related to the new process, because 7Nm EUV process further increases transistor density on the basis of the existing 7Nm, which lays a foundation for L3 cache increase.

According to TMSC, the performance of 7Nm + EUV process is improved by 10% compared with 7Nm process, energy efficiency is increased by 15%, and transistor density is increased by 20%. This improvement level is not the level of the new generation process, but the improved optimized version.

Editor in charge: WV

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