/AP / — Synopsys, Inc. (NASDAQ: SNPs) recently announced the launch of the industry’s first computeexpresslink support ™ (CXL ™) 2.0 to realize the performance breakthrough of data intensive system on chip (SOC). CXL is a new generation of open standard interconnection technology, which can establish a high-speed interconnection ecosystem among CPU, accelerator and memory expansion devices. The accelerator includes GPU, FPGA and specific accelerator solutions. This technology is based on mature pciexpress ® Architecture, and uses the physical layer and electrical interface of PCI Express 5.0.

Xinsi technology cxlvip is based on the universal verification methodology (UVM) architecture of the new generation SystemVerilog, which can simplify the integration in the existing verification environment, accelerate the simulation performance, effectively shorten the tuning time of the first test case, and allow users to run more test cases. Cxlvip combines the Verdi of Xinsi technology ® Protocol analyzer and performance analyzer also include coverage analysis and verification plan to accelerate verification convergence. In addition, validated designware ® The 16lane connection provided by cxlip can achieve high bandwidth and low latency, so it can support three CXL protocols (cxl.io, cxl.cache, CXL. MEM) and device types to meet different application scenarios.

Vikas Gautam, vice president of R & D of Xinsi technology verification technology team, said: “Xinsi technology’s memory consistency verification IP products include cxl2.0, cxl1.1 and ccix, which can support new applications with high data throughput requirements. We will continue to enrich industry-leading verification IP products and continue to work closely with standards organizations and flash memory suppliers, so that developers can quickly adopt and integrate the latest connectivity technologies.”

Jim Pappas, chairman of cxlconsortium, said: “it is an important direction for us to continuously develop CXL, an open standard connection technology, and improve the performance of the new generation data center”. We are very grateful to Xinsi technology for its support to the CXL alliance and its promotion of the application of CXL technology. “

Cxl2.0 protocol improves the fan out and pooling features in both the physical layer and the application layer. New features supported by cxl2.0 include:

CXL switching, supporting multiple logical devices (MLD)

IDE supporting cxl.io and cxl.cxl.cache/mem (Security)

Cxl2.0 devices can be negotiated during APN phase and hot plug, CXL enumeration is supported, and CXL devices are used as the endpoint of pciexpress

System level management is updated through QoS remote sensing technology, including function level reset, global continuous refresh, memory interpolation and consistency test

Supply and other resources

Synopsysvcvip subsystem supporting cxl2.0 / 1.1 specification is now available. Designwarecxlipsolution is also available at present.
Editor in charge: PJ

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