The complete designware die to die controller and PHY IP core solution can greatly improve performance, so as to realize efficient connection between bare chips in high-performance computing, AI and network SOC

Mountain view, California, June 10, 2021 / AP /–

Key points of this announcement:

  • The complete designware die to die IP solution, including controller, 112G usr / xSr and HBI PHY, supports bare chip differential and computing expansion
  • The error correction mechanism of the new die to die controller has replay and optional forward error correction functions, which can greatly reduce the bit error rate and realize a reliable die to die link
  • Low latency architecture supports AMBA Cxs and arm ® Neoverse ™ Efficient connectivity between coherent mesh networks

Xinsi technology provides a complete multi bare chip solution, using die to die IP, HBM IP and 3dic compiler to realize system level packaging integration

Synopsys, Inc. (NASDAQ: SNPs) recently announced the launch of a new designware ® The die to die controller IP core realizes a complete die to die IP solution together with the company’s existing 112G usr / xSr PHY IP core. The complete IP solution can provide developers with low latency and high bandwidth die to die connections to meet the needs of high-performance computing, artificial intelligence (AI) and network SOC for greater workload and faster data transmission. Designware die to die controller and PHY IP core are part of Xinsi technology’s multi bare chip solution. They are composed of HBM IP and 3dic compiler, which can accelerate SoC design requiring advanced packaging.

Jeff DEFILIPPI, director of product management, arm infrastructure business unit, said: “Interconnection technology is becoming more and more important for the next generation of high-performance and customized infrastructure SOC. Xinsi technology designware die to die controller has low latency and native support for AMBA Cxs, and can be easily integrated with arm coherent mesh network to provide our common customers with multi-chip IP solutions and provide higher expansion required for next-generation infrastructure computing Performance and operational options. “

Designware die to die controller has error correction mechanism, such as optional forward error correction and cyclic redundancy check, to achieve higher data integrity and link reliability. The flexible configuration of designware die to die controller supports AMBA ® Cxs and Axi protocols enable coherent and incoherent data communication, which can be easily integrated into arm based SoC and other high-performance SOC. Designware die to die controller supports up to 1.8tb/s PHY bandwidth and can realize powerful die to die connection to meet SOC’s demand for high-performance computing.

John koeter, senior vice president of IP marketing and strategy of Xinsi technology, said: “With the trend of bare chip splitting and decomposition, ultra short and ultra short distance links are needed to realize high data rate connection between bare chip chips. Xinsi technology’s complete designware die to die IP solution provides ultra-low delay controller and high-performance PHY, which has been adopted by many customers to assist developers to safely integrate high-quality IP into bare chip SOC while minimizing the cost Reduce integration risk. “

Xinsi technology’s extensive designware IP core combination includes logic library, embedded memory, IO, PVT monitor, embedded test, analog IP, interface IP, security IP, embedded processor and subsystem. In order to accelerate prototype design, software development and integrate IP core into chip, Xinsi technology IP accelerated plans to provide IP prototype design suite, IP software development suite and IP core subsystem. Our extensive investment in IP quality and comprehensive technical support enable designers to reduce integration risk and accelerate time to market.

Supply and resources

Designware die to die controller IP is now available to early adopters. Xinsi technology designware die to die usr / xSr PHY IP core has launched products suitable for 12NM, 7Nm and 5nm processes, and plans to launch 3nm process products. HBI PHY IP cores for 7Nm and 5nm processes are now available.

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