Mutual customers of both sides can obtain a complete 3dic solution “from preliminary planning to signing off” to deal with the complexity of hundreds of billions of transistors

Mountain view, California, December 8, 2021 / AP /–

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The unified 3dic platform can drive PPA optimization at the system level

Xinsi technology and Samsung Wafer Factory (hereinafter referred to as “Samsung”) strive to improve the innovation and efficiency of advanced node and multi bare chip packaging to meet the large demand of HPC, AI, automotive and 5g applications

Synopsys, Inc., NASDAQ: SNPs) recently announced that it has integrated 2.5D and 3D multi bare chip packaging collaborative design and analysis technology, and 3dic compiler platform has passed Samsung multi bare chip integration (MDI) ™) Process Certification to facilitate SOC innovation for computing intensive applications such as high-performance computing, AI and 5g. Based on this, mutual customers of both sides can efficiently manage complex 2.5D and 3D designs through a unified 3dic design platform, support hundreds of billions of transistor designs, and achieve better PPA goals and extended performance.

Sangyun Kim, vice president of design technology team of Samsung Electronics wafer factory, said: “Xinsi technology and Samsung are working together to simplify the way of multi bare chip design optimization through the analysis from early to full system implementation and signing off. The collaborative design and analysis of chip and advanced packaging based on Xinsi technology 3dic compiler platform once again proves that our close cooperation can provide customers with advanced productivity solutions and help them shorten turnover time And reduce costs. “

Multi bare chip integration refers to stacking and integrating multiple bare chips into a single package to meet the system requirements in PPA, functionality, overall dimension and cost. In this mode, terminal products can be modularized and flexibly combined to mix and match different technologies into solutions to meet different market segments or needs. 3dic compiler is a complete end-to-end solution, which can realize efficient multi bare chip design and whole system integration. It is built on the highly integrated fusion design platform of Xinsi technology ™ Based on the general and scalable data model, it supports the collaborative design and analysis of multi bare chip, and provides a unified and seamless integrated environment for 3D visualization, early design exploration, planning, specific implementation, design analysis and signing.

Shankar Krishnamoorthy, general manager of Xinsi technology chip implementation division, said: “The traditional 3D IC design process is cumbersome and needs repeated iterations. Realizing multi bare chip integration requires multiple tools and processes, which limits the engineering efficiency. In order to meet the needs of our customers for higher efficiency and greater expansion capacity, we made innovative innovations on 3dic compiler and provided a 3D silicon implementation integration platform from development to signing, further improving the new idea The leading position of science and technology in this field. Samsung and Xinsi technology cooperate closely to realize the verification of 3dic compiler in MDI process, and provide our common customers with a mature platform verified by streaming, so as to optimize their innovative multi bare crystal chip design and accelerate product launch. “

3dic compiler platform integrates starrc ™ Primetime ® Gold signature solution: krypton extracts parasitic parameters and static timing analysis (STA) for multi bare chip; Using ANSYS ® RedHawk ™- Electromigration / voltage drop (Emir) analysis, signal integrity / power integrity (Si / PI) analysis and thermal analysis are carried out by SC and HFSS technologies; Built in primesim ™ Continuum is used for circuit simulation, and IC validator is integrated ™ For design rule checking (DRC) and circuit layout verification (LVS); It also includes Xinsi technology TestMax ™ DFT solution supporting ieee1838 multi bare chip test design standard.

3dic compiler, as a part of fusion design platform of Xinsi technology, is connected with fusion compiler ™ The cooperative optimization of multi bare chip RTL to GDSII is realized by using scalable. In addition, the solution also provides designware ® Foundation, 112G usr / xSr die to die and hbm2 / 2E / 3 IP, siliconmax ™ In chip monitoring and sensing IP, and supports integrated optoelectronic technology. A wider range of solutions can be verified by Xinsi technology ® The platform provides hardware and software collaborative verification, power analysis and system physical prototype design. 3dic compiler platform and wider chip implementation product portfolio are silicon to software of Xinsi technology ™ Part of the strategy aims to help develop future oriented semiconductor and software products.

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