Mipi is divided into CSI (camara sensor interface) and DSI (display interface)

Electrical characteristics 1. Low power model 0-1.2v single terminal voltage; 2. High speed model 0.1-0.3 differential JEDEC

Xilinx only ultrascale + supports Mipi d-phy interface

UltraScale UltraScale+
PLL VCO range 600-1335MHz 750-1500MHz
IDELAY/ODELAY max PVT delay 1.25ns 1.15ns
HR banks Yes No
HD banks No Yes
MIPI D-PHY No Yes

If other types of FPGA need to support Mipi interface, there are two ways:

Resistance network; Refer to xapp894. It is required that the frequency is below 800m Hz and the wiring is within 30mm;

Bridge chip high performance metricom FPGA bridge metricom chip-mc20002;

At the 2015 annual exhibition of the National Association of broadcasters (NAB), fidus and inrevium jointly displayed a number of new products, one of which is the dual Mipi FMC development board. The development board is designed for system developers and researchers interested in Mipi csi-2 and DSI d-phy standards. Inserting tb-fmcl-mipi FMC card into LPC FMC connector is very common in many Xilinx FPGA and zynq SOC evaluation boards. At the same time, meticom mc20901 (cis-2) and mc20902 (DSI) transmission chips are used to convert between LVDS of FPGA or SOC and low-speed CMPs pin, Mipi csi-2 and DSI d-phy port at the speed of 2.5Gbps per channel. The following figure is the operation block diagram of the development board:

Xilinx FPGA supports two ways of Mipi interface

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