In some real-time data acquisition and information processing circuits, AD converters with high resolution and fast conversion speed must be used to meet the accuracy and speed requirements of data acquisition. MAX194 is a high-precision, high-speed 14 bit serial AD converter with sample and hold. MAX194 chip is applied in the subject practice, and good results are obtained. Because the output mode of MAX194 is serial output, which is different from the general parallel output mode, there are some matters needing attention when communicating with MC51 Series MCU. Here, the author introduces the problems and solutions encountered in the application.

1 working principle and structure

The working principle block diagram of MAX194 is shown in Figure 1. It is mainly composed of main DAC, control logic, comparator and calibration DAC. The main DAC is used to generate the analog signal compared with the input analog signal. Its internal structure is different from that of the DAC in general analog-to-digital converter. It does not use T-type resistance network, but is composed of capacitor array with binary weight (see Fig. 2). The analog electronic switch is controlled by the digital code of the digital quantity. When the code is 0, the switch is grounded, and when the code is 1, the switch is connected to the reference voltage. Thus, when D13 is 1 and others are 0, VA = VREF / 2; When D12 is 1 and others are 0, VA = VREF / 2; And so on until VA = VREF / 2 14 when d0 = 1 and others are 0. According to the superposition principle, the total equivalent potential is:

VA=d13VREF/2+d12VREF/2 2……+d0VREF/2 14

Working principle, performance and application design analysis of 14 bit serial AD converter MAX194 chip

Taking unipolar input as an example, the specific conversion process is as follows:

(1) Connect the free ends of the capacitor to AIN to charge the capacitor to obtain voltage Vin.

(2) Connect the highest capacitor to the reference voltage and the free ends of other capacitors to ground so that VA = vain, i.e. D13 = 1 and other bits are 0. At this time, VA = VREF / 2-vain. When VA “0” is vain “VREF / 2”, the output of the comparator is 1, and make D13 = 0 through control logic, otherwise make D13 = 1. After the highest capacitor is determined, if D12 = 1 and the rest are 0, VA = d13vref / 2 + d12vref / 2 2-vain.

(3) To determine the secondary high bit through the comparator and control logic, and so on. After 16 comparisons, the conversion can be completed (including two additional bits). It should be noted that the dummy capacitor in the figure is set to make the capacitor in front of it have weight, and it has no weight. The DAC composed of capacitor will make MAX194 have sample and hold function, that is, the circuit does not need to add sample and hold part.

In addition, MAX194 has its own calibration function, which can be calibrated when powered on. When the external environment changes (such as temperature change, power supply voltage change, etc.), it can also be manually reset to 0 for calibration.

2 pin arrangement and function

The pin arrangement of MAX194 is shown in Figure 3. It adopts 16 pin dip package, and the functions of each pin are as follows:

Pin 1 (BP / up / SHDN) is a three state input. If this pin is suspended, the analog signal is input in a bipolar manner; Unipolar input when connected to high level; 10 when connected to low level μ The off mode of a works.

Pin 10 (reset) stops working when it is low and starts calibration at the rising edge.

When pin 9 (conv) goes low, the A / D conversion begins.

Pin 7 (EOC) is the end of conversion output. The low level is output at the end of the conversion, and then becomes high at the beginning of the next conversion.

Pin 2 (CLK) is externally connected with conversion clock, and the maximum frequency is 1.7MHz; Pin 3 (SCLK) if the result is read after the conversion, it is read at the frequency of SCLK. It can be different from the frequency of CLK, up to 5MHz.

Pin 5 (dout) is the serial data output pin, which outputs the highest bit first.

Pin 8 (CS) is a chip select signal that allows serial output.

Pin 12 (Ref) is the reference voltage input, and the output range is 0 ~ 5V.

Pin 11 (AIN) is an analog input, and the input range is 0 ~ vrfef or – VREF ~ + VREF.

Pins 6 and 14 (dncd and agnd) are digital ground and analog ground respectively.

Pins 4 and 16 (vddd and vdda) are + 5V digital power supply and + 5V analog power supply respectively.

Pins 11 and 15 (vssd and vssa) are – 5V digital power supply and – 5V analog power supply respectively.

3 application circuit of MAX194

MAX194 can be widely used in industrial control, measurement, digital signal processing and so on.

Figure 4 shows the interface circuit between MAX194 and single sleep machine in boiler temperature measurement system, which connects CS to P2 Pin 7, and the software sends a chip selection signal. The time pulse CLK for conversion is generated by the ale pin of 89C51. The TXD of 89C51 is not gated to SCLK to be used as a clock for reading data.

There are two ways to read out the conversion results, one is to read out at the clock frequency of CLK during the conversion, and the other is to read out at the clock frequency of SCLK after the conversion. The author chooses to read the results after the conversion (the second method). After the conversion, when EOC becomes low and CS is also low, the highest bit is output on dout, and then other bits are output successively on the falling edge of SCLK. The maximum frequency allowed by SCLK is 5MHz. Fig. 5 is a timing diagram.

In the figure, tconv is the conversion time; TCSs is the time of CS falling mode edge; Tcsh is the time from the last falling edge of SCLK to the rising edge of CS.

4 precautions

When using the circuit in Figure 4 for interface design, the following points should be paid attention to;

(1) TCSs must be greater than 75 μ s. CS shall be set to zero first in the program, and then the conversion start signal shall be sent.

(2) The conversion start pulse must be synchronized with the conversion clock. For this purpose, at P1 An OR gate shall be added between 0 and ale and then connected to conv to ensure synchronization.

(3) When TXD is directly connected to SCLK, because 89C51 reads on the falling edge of TXD, and the first falling edge of TXD (SCLK) starts to output the secondary high order, the highest order will be lost. Therefore, an inverter can be connected between TXD and SCLK, so that when data is read in at the falling edge of TXD, dout can output data at the rising edge of TXD (the falling edge of SCLK). Because the read data and output data are time-sharing, this full data output mode of reading the highest bit first and then outputting the second highest bit is guaranteed.

(4) Because in the receive buffer SBUF, the storage order of data is:

d6d7d8d9d10d11d12d13

Therefore, the sequence should be rearranged in the program. Fig. 6 is the program block diagram. The specific program is as follows:

ADZHUAN:CLR PSW

CLR C

CLR P2. seven

MOV P0,#02H

MOV R1,#03H

SETB P1. 0

CLR P1. 0

SETB P1. 0

SETB P3. two

HERE:JB P3. 2,HERE

LOOP:MOV SCON,10H

WAIT1:JNB RI,WAIT1

MOV A,SBUF

MOV @R1,A

INC R1

DJNZ R0,LOOP

SETB P2. seven

LCALL EXCH

RET

EXCH:MOV R1,30H

MOV A,#00H

CLR C

MOV R7,#08H

LOOP0:XCH A,R1

RRC A

XCH A,R1

RLC A

DJNZ R7,LOOP0

MOV 32H,A

MOV R1,31H

MOV A,#00H

CLR C

MOV R7,#08H

LOOP1:XCH,A,R1

RRC A

XCH A,R1

RLC A

DJNZ R7,LOOP1

MOV 33H,A

RET

Responsible editor: GT

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