Ad7262 is a progressive approximation (SAR) analog-to-digital converter (A / D converter). It has two tracking and holding amplifiers, two 12 bit synchronous sampling a / D converters, two programmable amplifiers, two groups of comparators and two independent data output pins. It is applicable to the field of automotive control and weak signal detection applications requiring high synchronization and simple operation. Therefore, the principle and application of synchronous sampling MD converter ad7262 are introduced in detail.
2 Introduction to ad7262
2.1 main features
The ad7262 has High-Speed Low-Power synchronous sampling, up to 1 ms / s. Its internally integrated programmable amplifier PGA has 14 amplification gains to choose from. Two sets of comparators a, B, C and D are used as arithmetic units for motor control or various electrode sensors. Comparators A and B have the characteristics of low power consumption, and comparators C and d have the characteristics of high speed. The dual channel differential input has simultaneous sampling and a / D conversion, and the input impedance is greater than 1G Ω. Single power supply + 5 V supply. PGA gain is 2, – 3 dB, bandwidth is 1.7 MHz, and SNR is 73 db; When the gain is 32, the signal-to-noise ratio is 66 dB. Input DC leakage current ± 0.001 μ A. The offset drift is 2.5 μ V／℃。 With serial peripheral interface SPI, compatible with QSPI, microwire and DSP. The device has a variety of energy-saving modes, dynamically matches the required internal modules, and has two working modes: register control and pin drive.
2.2 pin function
Avcc: analog power input, 4.75 ~ 5.25 V;
CA_ CBVCC／CC_ CDVCC: power input terminal of comparator, 2.7 ~ 5.25 V;
CA_ CB_ GND／CC_ CD_ GND: ground input of comparator;
VA + / VA -, VB + / VB -: differential analog input of a and B channels of a / D converter;
Vrefa / vrefb: reference voltage input and output terminals of a and B channels of a / D converter;
SCLK: serial clock, SPI communication clock, which is also the clock source of a / D conversion process;
Cal: initialize the internal offset calibration logic input;
PD2: energy saving mode selection logic input;
PD1: energy saving mode selection logic input;
Pd0 / DIN: energy saving mode selection logic input, and it is the data input terminal in register control mode;
CS: chip selection input terminal;
Ca + / Ca -, CB + / CB -: differential inputs of comparators A and B;
CC + / CC -, CD + / CD -: differential inputs of comparators C and D;
Agnd: Analog ground input terminal;
DGND: digital ground input terminal;
Couta ~ coutd: CMOS push-pull output of comparator. When vdrive is used, it is digital output terminal;
Douta / doutb: A / D conversion serial data output terminal;
G0 ～ G3: gain multiple logic input. When it is all at low level, it is the working mode of register control;
Vdrive: logic power input, 2.7 ~ 5.25 V;
Refsel: reference voltage selection terminal. Internal reference voltage is used for high level and external reference voltage is used for low level.
2.3 internal structure
Figure 1 shows the internal structure of ad7262. After the two differential signals are synchronously sampled and amplified by their respective PGA, they enter the tracking holder. At this time, the control logic controls two 12 bit successive approximation A / D converters to realize analog-to-digital conversion. Finally, the output driver drives and outputs them to douta and doutb respectively.
In pin driving mode, G0 ~ G3 must have at least one high level. The external G0 ~ G3 determines the magnification of PGA. The three port levels of PD2 ~ pd0 control the use or shutdown of its internal comparator and 12 bit a / D converter modules. Under the register control mode, PD2, PD1, G0 ~ G3 are all low levels. Pd0 / DIN is the data input terminal, which is used to write relevant control registers and dynamically configure magnification, calibration and energy-saving modes. Ad7262 outputs the conversion result with the complement of 2.
2.4 automatic calibration
Automatic calibration is one of the main features of ad7262. Use the cal pin to calibrate the device offset. Set cal to high level and initialize the calibration value at the next falling edge of CS. The completion of offset calibration requires a complete conversion cycle, including 19 SCLK cycles after the falling edge of CS. If necessary, the cal can maintain a high level for more than one conversion cycle, and the ad7262 continues calibration at this time. You can also use the initial calibration value of the control register and set the cal bit of the control register to 1. Note that at the next falling edge of CS, calibration will be initialized and the current conversion of ad7262 will be meaningless. Its a / D converter must be in working state to complete internal calibration.
Channels A and B of a / D converter have independent external gain registers to calibrate the signal gain. The gain calibration register has 7 bits. Change the register to compensate for the gain. MSB is the symbol bit, and the other 6 bits are the storage gain multiple, which is used to adjust the range of analog input signal, and its calibration accuracy is 1 / 4 096.
3 typical applications
3.1 hardware design
Figure 2 shows the typical application circuit of ad7262 and arm processor LPC2378 to collect electrode A and B current and electrode m and N voltage in DC exploration. The metal film resistance is used as the sampling resistance to improve the measurement accuracy. Since the voltage between electrodes a and B is the electrode voltage supplying power to the earth, which is generally greater than 100 V, there is a high-voltage isolation circuit in the front-end electrode, and the resistance value of the sampling resistance is generally less than 100 Ω. The ad7262 operates in register control mode. Under the control timing of SCLK provided by p0.15 of LPC2378, write relevant data to the control register of ad7262 through p0.18. After CS enters the low-level state, first write the relevant register data by p0.18, then start sampling and holding and convert the output. When writing to the register, douta and doutb outputs are three states.
The main communication mode of ad7262 is SPI four wire type. Since ad7262 cannot control when to communicate, it can only work in slave mode. P0.15 of the main controller LPC2378 provides the communication clock signal SCLK. CS is chip selection input. Douta or doutb is the data output of SPI. The data input terminal of SPI is pd0 / din. During circuit design, various dynamic configurations are realized by writing relevant data to ad7262 through LPC2378. Fig. 3 and Fig. 4 are sequence diagrams of serial interface reading and writing. The serial clock SCLK provides the control of conversion clock and transmission information after ad7262 conversion. For two on-chip A / D converters, the ad7262 has two corresponding output pins. Data is read from douta and doutb of ad7262. The user can choose one of them to output data.
At the falling edge of CS, the tracking holder is in hold mode. At this time, sampling and rotation
The analog input is initialized at the same time. This requires at least 19 SCLK cycles. When the falling edge of the 19th SCLK arrives, ad7262 returns to the tracking mode and sets douta and doutb to enable. The data stream consists of 12 bits, with MSB first. The conversion result MSB is read by the microcontroller on the falling edge or rising edge of the 20th clock SCLK at the falling edge of the 19th cycle of SCLK. The rising or falling edge depends on the frequency of the SCLK used. If the maximum frequency of SCLK is 40 MHz, the data reading time is 23 ns, resulting in a 2 ns setup time. The 2 ns setup time cannot match the microcontroller. In this case, it is necessary to start reading data at the rising edge of the clock SCLK. In this way, the MSB bit of the conversion result is delayed by 15 ns at the falling edge of the 19th SCLK, and is read out at the rising edge of the 20th cycle SCLK. By analogy, the A / D converter outputs LSB at the falling edge of the 30th SCLK and reads it at the rising edge of the 31st SCLK. Conversely, if SCLK is 32 MHz, the falling edge reads data. In the design, the communication clock frequency of SPI (p0.15 of LPC2378) is less than 32 MHz, so LPC2378 reads and writes data on the falling edge of the clock. In order to improve the accuracy and stability of the system, a coupling capacitor with a certain resistance can be added.
3.2 software design
Ad7262 contains six registers, which are the result register of a / D converter, control register, internal offset register of a / D converter A and B, and external gain register of a / D converter A and B channels. The control register has 12 bits in total, of which RD3 ~ rd0 are register selection bits.
Since both LPC2378 and ad7262 are compatible with SPI interface, they only need to be programmed according to the sequence diagram. In addition, LPC2378 has many other types of interfaces, so it is easy to realize networking. See Figure 5 for the detailed flow.
Note in software design: cal pin must be kept at least 2 before CS is low μ S high level to ensure the accuracy of calibration in the first conversion cycle. If the CAL is low during this period, the calibration results will be inaccurate. However, if it continues to be high, the next calibration conversion is accurate. In addition, in the process of a / D conversion, if the cal has a high level, the conversion result will also be incorrect. Ad7262 is calibrated before a / D conversion during measurement. In the measurement process, calibrate first and then sample and hold. And programming to write registers should be separated in timing. In addition, using SPI interface, only hardware reset is not enough, and software reset is also used to ensure the correctness of reading and writing data. In practical application, the digital and analog parts should be isolated from the ground wire. The whole software part is completed by serial port reading and writing registers.
Compared with other a / D converters, ad7262 not only has the characteristics of fast conversion speed, simple interface, low power consumption and strong control function, but also has the characteristics of embedded PGA, automatic calibration and synchronous sampling. It is suitable for signal detection, control and motor control systems of various electrode sensors with different signal strength levels. At present, the system has been successfully applied to the electrical method experimental instrument of physical exploration to realize the electrode synchronous voltage measurement of A-B and M-N, and the effect is good.
Responsible editor: GT