1. Main features of adc10065

Adc10065 is a low-power, single power supply CMOS analog-to-digital converter launched by national semiconductor. When powered by 3V single power supply, the chip can convert analog signals into accurate 10 bit digital signals at the sampling rate of 65msps, and the power consumption is only 68.4mw, and the power consumption in standby mode is only 14.1mw. The adc10065 chip adopts a differential bus structure with data error correction function. Therefore, it can provide excellent dynamic performance with minimal power consumption. The device can be widely used in ultrasonic and image acquisition, cellular base station / communication receiver, sonar / radar, xDSL, WLAN, data acquisition system and DSP front-end.

The main characteristics of adc10065 are as follows:

● 3V single power supply;

● full scale input swing can be selected from four input signals: 2.0vp-p, 1.5vp-p, 0 or 1.0vp-p;

● 400mhz-3db input bandwidth;

● have static working mode;

● with on-chip reference source and sample and hold amplifier circuit;

● output in binary complement data format;

● adjustable output drive is suitable for 2.5V and 3.3V series logic device interfaces.

The following are the main parameters of adc10065:

● resolution: 10bits;

● conversion rate: 65msps;

● fpbw (full power bandwidth): 400MHz?

● DNL (differential nonlinearity): ± 0.3lsb;

● SNR (signal-to-noise ratio fin = 32mhz): 59.3db;

● SFDR (when error free dynamic range fin = 32mhz): – 80dB;

● data delay: 6 clock cycles;

● reference voltage: + 3.0V;

● power consumption at 65Mhz: 68.4mw.

2. Pin function

Working principle and application circuit analysis of CMOS analog-to-digital converter adc10065

Figure 1 shows the pin arrangement of adc10065. The device is packaged with 28 pin tssop. The basic functions of each pin are as follows (PIN number in brackets):

Vin -, VIN + (12, 13): analog signal input terminal. Under 1.2V reference voltage, the full-scale input swing is 1.0vp-p. During single end operation, VIN + can be connected with VCOM.

VREF (6): the reference voltage (1.5V) pin should pass a 1 when used μ The bypass capacitor of F is connected to vssa.

Vreft, VCOM, vrefb (7, 4, 8): vreft and vrefb are only high impedance reference bypass pins, while VCOM can be used to set the input common voltage VCM. These three pins should be connected to 0.1 μ Bypass capacitance of F.

CLK (1): digital clock input. The input frequency range is 10MHz ~ 65Mhz, and the input is valid at the rising edge of the clock.

DF (15): when this pin is at high level, the output is binary complement; when this pin is at low level, the output is offset binary code.

STBY (28): static standby mode pin. At high level, the device turns to standby mode.

IRS (5): select pin for input range. When this pin is connected to vdda, the full-scale input swing is 2Vp-p, 1.5vp-p when connected to vssa and 1Vp-p when suspended.

D0 ~ D9 (16 ~ 20, 23 ~ 27): data output terminal. D0 is the least significant bit of binary output data, and D9 is the most significant bit.

Vdda (2, 9, 10): positive pole of analog power supply. It needs to be connected with a 3V DC power supply and a 0.1 μ Bypass capacitance of F to analog ground. The capacitance should be close to these pins, and the distance should not exceed 1cm. At the same time, a parallel 4.7 μ F capacitance to analog ground.

Vssa (3, 11, 14): Analog ground.

VDDIO (22): positive terminal of digital power supply. The foot also applies a 0.1 μ F capacitor bypass to digital ground simultaneously with a 4.7 μ The capacitance of F is connected in parallel to digital ground. The voltage on this pin cannot exceed the vdda voltage by more than 300mV.

Vssio (21): digital ground. When in use, it should be connected with digital ground and away from analog ground.

3. Working principle

Figure 2 is the internal structure block diagram of adc10065.

The device consists of seven parts: sample and hold, nine level differential circuit, clock control, digital error correction, band gap precision power supply, output buffer and tubular data line. According to the different states of IRS, the analog signal with peak to peak value of 1V, 1.5V or 2V can be selected at the differential input, in which the center value is VCM / 2 and the phase difference is 180 °. However, the differential input mode can make the system obtain better performance. The only sample and hold stage in the chip can provide 400MHz full power bandwidth, and the multi-stage differential circuit of digital error correction can ensure low power consumption while providing excellent dynamic performance. The + 1.2V precision reference power supply inside adc10065 can be used to set the input signal peak range of the chip. When the accuracy requirement is high, the external reference power supply can also be used. Its 10 bit digital output format can be offset binary code or binary complement.

Figure 3 shows the transmission characteristics of adc10065.

4. Application circuit

Figure 4 shows a typical differential input application circuit of adc10065. In the figure, the two analog signal inputs VIN + and VIN – of adc10065 form a differential input pair, and the common mode pin VCOM is used to set the common input voltage VCM. The working reference voltage of adc10065 is 1.2V, but it still has excellent performance at 0.8 ~ 2.0V. A lower voltage can reduce the signal-to-noise ratio, which is 0.1 on the three bypass pins VREF, vreft and vrefb μ F capacitor is mainly used to reduce noise current. Since the switching action inside the analog input terminal will consume a certain amount of energy and add a certain noise signal, an 18 Ω resistor should be connected in series at each input terminal and a 25pf capacitor should be connected at the same time. These components should be placed close to the chip as far as possible. The input terminal is the most sensitive part of the system and the last opportunity for filtering.

Since the CLK signal is used to control the sampling process, the signal shall be stable and low jitter, the range shall be 10MHz ~ 65Mhz, the rise / fall time shall be less than 2ns, and its lead wire shall be as short as possible without crossing any lead wire, especially 90 °. CLK signal sometimes drives the on-chip state machine. If it is interrupted or the frequency is too low, the charge of the capacitor in the chip will discharge, which may reduce the accuracy of output data. The duty ratio of CLK also has a great impact on the performance of a / D converter. Generally, it is required to be 40% ~ 60%, preferably 50%.

Adc010065 has a 10 bit TTL / CMOS compatible output. A simple way to capture one bit of valid data is to latch data on the rising edge of the clock. When driving the high capacitance bus, be particularly careful. Due to the charging effect of the capacitor, the larger the driving capacitance is, the greater the current passing through VDDIO and vssio instantaneously. This charging spike pulse can cause on-chip noise and may be coupled to the analog circuit, so as to reduce the dynamic performance of the chip. In addition, the bus capacitance can also increase the output delay time, which makes it difficult to latch the output data. In order to reduce noise, the load current at the data output must be minimized. For this purpose, a primary data buffer can be added between the ADC output and other external circuits.

Responsible editor: GT

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