Today's integrated circuits are running faster than ever. The increased operating speed results in a highly dynamic power demand from the power supply, which poses a challenge during testing when you are powering with a programmable power supply. High-speed current waveforms can cause IC voltage drops. If severe enough, the voltage drop can reset the microprocessor or cause abnormal test results. This article explains why the voltage drop occurs, provides various methods to achieve the lowest possible voltage drop by selecting the optimal load leads and power supply, and using local bypassing.

**Select Programmable Power Supply**

Traditionally, for the best output voltage regulation you would use a linear power supply. However, linear power supplies tend to be very large, expensive, and extremely inefficient at higher current levels. Recent advances in switching power supply technology have made it possible to replace linear power supplies with switching power supplies in high-performance applications. Switching power supply designers are faced with the seemingly contradictory goals of low output noise, fast transient response, low cost, and high density. Achieving low output noise is usually achieved through multiple stages of filtering or the use of larger filter components, both of which result in higher cost, lower power density, and slower transient response. More advanced power supplies employ higher switching frequencies, better filter designs, and more complex control topologies to optimize all criteria. When selecting a power supply for an IC test application, voltage transient response specifications and output impedance characteristics must be checked to ensure good performance.

**Optimize load wiring**

In many cases, physical constraints force you to place the power supply several feet away from the IC test board, requiring at least several feet of load lead wiring. Load lead wiring impedance quickly reduces the source impedance of the IC. Almost all programmable power supplies provide a sense lead input where you can select the voltage regulation point by connecting the voltage sense lead at this location. In this application, the sensing point should be as close to the IC as possible. However, the voltage regulation loop can only suppress voltage transients at this detection point within its control bandwidth. Therefore, if the current transient rise time is fast enough, a voltage transient will occur at this sensing point. figure 1.

Figure 1: Simplified power supply output impedance and load lead impedance

Let's examine a 25A application with a 5A transient, where the power supply is set to 2.5V and connected to an IC test board via a 5-pin 14-AWG wire. Since this is a low voltage application, voltage undershoot greater than 100 mV is generally not acceptable. The 14-AWG wiring has a resistance of 2.5 mΩ per foot, resulting in 25 mΩ for the round-trip connection between the power supply output and the IC test board.

The supply voltage control loop will compensate for the calculated 125 mV drop after a period of time commensurate with its bandwidth. However, at the same time, the IC will experience a voltage drop of 125mV. In this application, the effect of load lead resistance alone is enough to cause an unacceptably short drop on the test board. However, load lead inductance is another major cause of voltage drop. It is not uncommon for a test board to ramp up a 5A transient within 10 µs. This high current rate of change results in a constant voltage drop across the leads during the current ramp. The load lead inductance varies depending on the position of the positive and negative leads. Using an approximation of the inductance, you can estimate the voltage drop. In most cases, a 250nH/ft inductor is a good model for wiring without twisting loads.

A result of 1.375 V is not acceptable. As mentioned earlier, the voltage regulation loop of the power supply will detect this voltage transient and adjust the output of the power supply as necessary to maintain a steady 2.5 V on the test board. However, even with a good power supply, this process can take up to 1 millisecond. To reduce lead inductance effects, force leads are tightly coupled together by tying them together at regular intervals or simply twisting them together. Twisted leads also provide the added benefit of better resistance to other magnetic fields that may exist due to different load leads carrying large current transients. A good model for twisted pair is the 170-nH/ft inductor. The inductor includes positive and negative lead inductance effects. Recalculated using twisted pair:

Although the voltage drop has improved, the overall results are not yet acceptable. This can be further improved by running parallel cables. For example, connecting four twisted pairs in parallel reduces the resistance and inductance by a factor of 4.

The 100 mV target is still out of reach, especially when we consider that the power supply contributes additional transient voltage drops in response to changes in output current. More specialized routing options such as custom coaxial or flat wire cables can increase inductive effects to as low as 10 nH/ft. However, these options are expensive and not readily available. Another option is low impedance energy storage very close to the test board.

**Use local bypass capacitors**

The power supply can't compensate for the voltage drop across the load leads and its output fast enough, so you need a local energy source, as shown in Figure 2. Capacitors are great for providing low impedance at high frequencies to complement the low impedance provided by power supplies at low frequencies. There are many different capacitor technologies available, and finding the right combination of parts or components can be difficult. Ceramic capacitors are ideal for high frequency bypassing at low voltages. However, even with recent advances in ceramic capacitor technology, they cannot match the high density and low price of aluminum electrolytic and conductive polymer aluminum solid electrolytic capacitors. The equivalent series resistance of the bypass network is an important parameter because it appears in series with the capacitor and can significantly reduce the efficiency of the bypass network.

The interaction between the supply voltage control loop, load lead network, and bypass capacitors can be a bit complicated. However, some simple approximations can help you choose an initial value for the capacitor. The process is as follows:

1. Calculate the peak network impedance. Use the following expression to determine the required peak impedance of the load lead network and bypass capacitor:

2. Calculate the bypass capacitor value. Set the desired peak impedance to an expression equal to the characteristic impedance of the LC tank formed by the load lead inductance and bypass capacitance. Solve the expression for the capacitance value:

Figure 2: Load lead network with bypass capacitors

3. Calculate the resonant frequency of the tank circuit. The output impedance of the power supply you use must be lower than the characteristic impedance of the LC tank; otherwise, the calculations you perform will not correctly predict system behavior. Power supply output impedance decreases with frequency. In cases where the output impedance of the power supply is higher than the desired peak impedance, the resonant frequency is chosen to be equal to the frequency at which the output impedance of the power supply is less than or equal to Z peak . The resonant frequency must be lowered by choosing a larger bypass capacitor.

4. Select the desired capacitor ESR to ensure proper damping of the LC tank. Proper damping of the resonant tank is critical because poorly damped circuits tend to ring and also have destabilizing effects on the power supply control loop. The combination of load lead resistance and capacitor ESR will act to dampen the resonant tank. We will set the damping ratio to 0.5 to achieve faster response and lower peak voltage by equating the tank resistance to the characteristic impedance of the LC tank.

Since it may not be possible to find capacitors with the correct capacitance and ESR, you can use parallel combinations of capacitors with different values and ESRs to obtain the desired parameters.

**result**

Figure 3 shows the transient voltage response observed across the load using the Keysight N7950A dynamic DC power supply. It is ideal for low voltage, high current operation and very low output impedance, making it ideal for this application. The light blue traces represent four twisted pairs without local capacitors. Dark blue is the response of adding a 530-µF capacitor, as calculated in Equation 7. Increasing the capacitance by a factor of 4 and decreasing the tank impedance by a factor of 2 results in red.

Figure 3: Actual measurements of the N7950A with and without local capacitance storage

generalize

This article explores the challenges of providing stable voltage to highly dynamic loads using a power supply located several feet away from the device under test. Although load lead impedance can severely degrade the transient response performance of high performance power supplies, by taking mitigation measures you can achieve the desired performance on the device under test. Techniques such as twisting the load lead wiring to minimize the loop area formed between the power and return wires, and using flat copper wire or heavy gauge coaxial cable can significantly reduce load lead inductance. Properly sizing the bypass capacitor network at the DUT can further improve voltage level stability in the face of fast current transients generated by the DUT.