Synchronous sequential logic means that the value of the register group representing the state can only be changed at the time when the unique trigger condition occurs. One example is a state machine that can only be triggered by a positive or negative edge of a clock. Always @ (posedge clock) is a trigger condition of synchronous sequential logic. It means that the re assignment of register variables in the begin end block controlled by always can only happen at the positive edge of clock.
Asynchronous sequential logic means that the trigger condition is composed of multiple control factors, and the jump of any factor can cause trigger. The clock inputs of a register group that records state are not all connected to the same clock signal. For example, asynchronous sequential logic is triggered by linking the output of one trigger to the clock side of another trigger.
The synthesis module designed with Verilog HDL must avoid using asynchronous sequential logic. This is not only because many synthesizers do not support the synthesis of asynchronous sequential logic, but also because it is really difficult to control the risks and competitions caused by composition logic and delay by using asynchronous sequential logic. When the complexity of the circuit increases, asynchronous sequential logic cannot be debugged. The slight change of process will also cause the failure of asynchronous sequential logic circuit. Because of the random trigger condition in asynchronous sequential logic, it may happen at any time, so the output of register group recording state may change at any time. The second trigger occurs when the trigger input in synchronous sequential logic can maintain at least one clock. This is a very important difference, because we can use the time of this clock to create a stable and reliable condition for circuit state change before the next trigger signal comes.
Therefore, we can conclude that synchronous sequential logic has more reliable and simpler logical relations than asynchronous sequential logic. If we make it mandatory to design a synthesis state machine with Verilog, we must use synchronous sequential logic. With this precondition, it is possible to realize the synthesizer of automatically generating circuit structure. Because this greatly reduces the complexity of the integrated tool and creates conditions for the maturity of this tool. It also creates the conditions for Verilog integrated code porting between various processes and FPGA.
Verilog RTL level synthesis is based on this provision.
We will elaborate on the differences between synchronous and asynchronous sequential logic.
In the synchronous logic circuit, the trigger signal is the positive or negative edge of the clock, and the input and output of the trigger are completed by two clocks. The positive (or negative) edge of the first clock is used to prepare for the input. There is enough time to stabilize the input during the period from the arrival of the positive (or negative) edge of the first clock to the arrival of the positive (or negative) hop edge of the second clock. When the second clock’s positive edge (or negative edge) arrives, the condition created by the previous clock edge is stable, so the next state can be output correctly.
If the register group is input and output under the positive (or negative) jump edge of the same clock, it is likely that the next state will be output when the input condition is not determined due to the delay of the gate, which will lead to logic disorder. It is safe and reliable to use the previous clock to create trigger conditions for the next clock. But this work mode needs a premise: the delay of the combinational circuit used to determine the next state and the difference between the clock and each trigger must be less than the width of a clock cycle. Only by satisfying this premise can we avoid logical disorder. In the realization of practical circuit, many effective measures have been taken to ensure this condition
(1) When routing the global clock network, try to make the clock of each branch consistent;
(2) The balanced tree structure is adopted, and buffers are added in each stage to synchronize the clocks arriving at each trigger. (as shown in Figures 1 and 2)
In the post simulation, if the logic is different from the expected design, the clock frequency can be reduced, which may eliminate the instability caused by delay and risk competition at the input end of flip-flop caused by too fast clock, so as to make the logic correct.
In combinational logic circuits, the input of multiple signals makes it easy to produce competitive risks when the signals change at the same time. Here is an example of a simple combinatorial logic: C = A & B;
The asynchronous change of a and B makes C produce a pulse. This result may not be consistent with the original design idea, but if we can take the result of combinatorial logic after the value of C is stable for a period of time, we can avoid competition and risk. Synchronous sequential logic uses the hop edge time of the last clock (setting the register as the input of the combinational logic) to prepare for the setting of the next clock’s hop edge time (setting the next register as the output of the combinational logic). As long as the clock cycle is long enough, a stable setting condition can be obtained at the hop edge time of the next clock Store reliable data in.
It is impossible to do this with asynchronous circuits. Therefore, asynchronous sequential logic should be avoided in practical design. If we use the method of compensation to avoid competition and risk, it will cost a lot of manpower and material resources. It is also impossible to make the Verilog HDL code and the circuit module structure that has passed the simulation test to have the possibility of intellectual property rights, because the subtle change of process may make the circuit unable to work normally. It is obvious that the use of asynchronous sequential logic will bring hidden trouble in design. It is impossible to design a state machine that can operate and control the direction switch of data flow strictly according to the same time rhythm. The state machine which can precisely control the data flow switch according to the clock beat is the synchronous finite state machine. It is the core of data flow control in the process of algorithm calculation. The reasonable configuration of computing structure and the improvement of operation efficiency are closely related to the design of algorithmic state machine. We can master the design of complex algorithm system skillfully only by reading the information about computer architecture and through a lot of design practice.