Today’s integrated circuits run faster than ever before. The increased operating speed will lead to a highly dynamic power demand of the power supply, which poses a challenge during the test when you use a programmable power supply. High speed current waveform will cause the voltage drop of integrated circuit. If severe enough, the voltage drop may reset the microprocessor or cause abnormal test results. This article explains why voltage drops occur and provides a variety of ways to achieve the lowest possible voltage drop by selecting the best load lead and power supply and using local bypass.
Select programmable power supply
Traditionally, to achieve optimal output voltage regulation, you use a linear power supply. However, linear power supplies are often very large, expensive and inefficient at high current levels. The latest development of switching power supply technology makes it possible to replace linear power supply with switching power supply in high-performance applications. Switching power supply designers are faced with seemingly contradictory goals of low output noise, fast transient response, low cost and high density. Low output noise is usually achieved by multistage filtering or using larger filter components, both of which will lead to higher cost, lower power density and slower transient response. More advanced power supplies use higher switching frequency, better filter design, and more complex control topology to optimize all standards. When selecting power supply for IC test application, voltage transient response specification and output impedance characteristics must be checked to ensure good performance.
Optimize load wiring
In many cases, physical constraints force you to place the power supply a few feet away from the IC test board, requiring at least a few feet of load lead wiring. The load lead wiring impedance will quickly reduce the source impedance of the IC. Almost all programmable power supplies provide sensing lead input, and you can select the voltage regulator node by connecting the voltage sensing lead at this position. In this application, the sensing point should be as close to the IC as possible. However, the voltage regulation loop can only suppress the voltage transient at the detection point within its control bandwidth. Therefore, if the current transient rises fast enough, a voltage transient will occur at the sensing point. Figure 1.
Figure 1: simplified power output impedance and load lead impedance
Let’s examine a 25A application with 5A transients, where the power supply is set to 2.5V and connected to the IC test board through 5-pin 14-awg wiring. Since this is a low voltage application, voltage overshoot greater than 100 mV is usually unacceptable. The 14-awg wiring has a resistance of 2.5 m Ω per foot, resulting in a resistance of 25 m Ω for the round-trip connection between the power output and the IC test board.
The supply voltage control loop will compensate for the calculated 125 MV voltage drop after a period of time commensurate with its bandwidth. However, at the same time, the IC will experience a voltage drop of 125mv. In this application, the effect of load lead resistance alone is sufficient to cause an unacceptable short-term drop on the test board. However, the load lead inductance is another major cause of voltage drop. It is not uncommon for the test board to ramp up 5A transient within 10 µ s. During the current ramp, this high rate of current change results in a constant voltage drop across the lead. The load lead inductance varies according to the position of the positive and negative leads. Using the inductance approximation, you can estimate the voltage drop. In most cases, a 250nh / ft inductor is a good model for non torsional load wiring.
The result of 1.375 V is not acceptable. As mentioned earlier, the voltage regulation loop of the power supply will detect this voltage transient and adjust the output of the power supply as needed to maintain a stable 2.5 V on the test board. However, even with a good power supply, this process may take up to 1 millisecond. In order to reduce the inductive effect of the leads, the force leads are closely coupled by tying them together at fixed intervals or simply twisting them together. Twisted leads also provide an additional benefit of better resistance to other magnetic fields that may exist due to high current transients carried by different load leads. A good model of twisted pair is 170 NH / ft inductor. The inductor includes positive and negative lead inductance effect. Recalculate with twisted pair:
Although the voltage drop has improved, the overall results are not acceptable. It can be further improved by parallel cable laying. For example, connecting four twisted pairs in parallel will reduce the resistance and inductance by four times.
The target of 100 mV is still out of reach, especially when we consider that the power supply will contribute additional transient voltage drop in response to the change of output current. More specialized cabling options such as custom coaxial or flat cable can increase the inductance effect as low as 10 NH / ft. However, these options are expensive and difficult to obtain. Another option is low impedance energy storage very close to the test board.
Use local bypass capacitor
The power supply cannot compensate the voltage drop on the load lead and the voltage drop on its output fast enough, so you need local energy, as shown in Figure 2. Capacitors are very suitable for providing low impedance at high frequency to supplement the low impedance provided by the power supply at low frequency. There are many different capacitor technologies available, and finding the right combination of components or components can be difficult. Ceramic capacitors are well suited to provide high frequency bypass at low voltage. However, even with the latest development of ceramic capacitor technology, they can not be comparable with the high density and low price of aluminum electrolysis and conductive polymer aluminum solid electrolytic capacitors. The equivalent series resistance of the bypass network is an important parameter, because it appears in series with the capacitor, which will significantly reduce the efficiency of the bypass network.
The interaction between the supply voltage control loop, the load lead network and the bypass capacitor may be a little complex. However, some simple approximations can help you choose the initial value of the capacitor. The process is as follows:
1. Calculate the peak network impedance. Determine the required peak impedance of the load lead network and bypass capacitance using the following expression:
2. Calculate the bypass capacitance. Set the required peak impedance to an expression equal to the characteristic impedance of the LC channel formed by the load lead inductance and bypass capacitance. Expression for solving capacitance value:
Figure 2: load lead network with bypass capacitor
3. Calculate the resonant frequency of the channel. The output impedance of the power supply you use must be lower than the characteristic impedance of the LC channel; Otherwise, the calculations you perform will not correctly predict system behavior. The power output impedance will decrease with the decrease of frequency. When the power output impedance is higher than the required peak impedance, select the resonant frequency to be equal to the frequency when the power output impedance is less than or equal to Z peak. The resonant frequency must be reduced by selecting a larger bypass capacitor.
4. Select the required capacitor ESR to ensure proper damping of LC resonant circuit. Proper damping of the resonant circuit is crucial, because the circuit with improper damping will tend to ring and will also have an unstable impact on the power control circuit. The combination of load lead resistance and capacitor ESR will damp the resonant circuit. We will achieve faster response and lower peak voltage by equating the channel resistance to the characteristic impedance of the LC channel and setting the damping ratio to 0.5.
Since it may not be possible to find a capacitor with the correct capacitance and ESR, you can use a parallel combination of capacitors with different values and ESR to obtain the required parameters.
Figure 3 shows the transient voltage response observed on the load when using keysight n7950a dynamic DC power supply. It is very suitable for low voltage, high current operation and very low output impedance. The light blue trace represents four twisted pairs without local capacitors. Dark blue is the response of adding 530 – µ f capacitor, as calculated in formula 7. When the capacitance is increased by 4 times, the channel impedance is reduced by 2 times, and the result is displayed in red.
Figure 3: actual measurement of n7950a with and without local capacitive storage
This paper discusses the challenge of using a power supply a few feet away from the equipment under test to provide stable voltage for high dynamic loads. Although the load lead impedance will seriously reduce the transient response performance of high-performance power supply, you can achieve the required performance on the equipment under test by taking mitigation measures. Techniques such as twisting the load lead wiring to minimize the loop area formed between the power supply and return line, and using flat copper wire or large-size coaxial cable can significantly reduce the load lead inductance. Facing the fast current transient generated by the device under test, properly adjusting the size of the bypass capacitor network at the device under test can further improve the voltage level stability.