MII (media independent interface)
MII is the media independent interface, which is the Ethernet industry standard defined by ieee-802.3. It includes a data interface and a management interface between MAC and PHY (Figure 1). The data interface includes two independent channels for transmitter and receiver respectively. Each channel has its own data, clock and control signal. A total of 16 signals are required for the MII data interface. Management interface is a dual signal interface: one is clock signal, the other is data signal. Through the management interface, the upper layer can monitor and control PHY. MII management interface has only two signal lines. The configuration and status data is written/read to/from the PHY via the MDIO signal.
MII standard interface is used to connect Fast Ethernet MAC block and PHY“ “Media independent” indicates that any PHY device can work normally without redesigning or replacing MAC hardware. The equivalent interfaces of MII at other rates are AUI (10M Ethernet), gmii (Gigabit Ethernet) and XAUI (10 Gigabit Ethernet).
The MII bus specified in IEEE802.3 is a general bus used to connect different phys with the same network controller (MAC). The network controller can use the same hardware interface with any PHY
GMII （Gigabit MII）
Gmii uses 8-bit interface data, working clock 125MHz, so the transmission rate can reach 1000Mbps. At the same time, it is compatible with the 10 / 100 Mbps working mode specified by MII.
Gmii interface data structure conforms to IEEE Ethernet standard. The interface is defined in IEEE 802.3-2000.
Gtxclk — Gigabit TX. Clock signal of signal (125MHz)
Txclk — 10 / 100M signal clock
[TXD [7.. 0] – sent data
TXEN — transmitter enable signal
Txer — transmitter error (used to destroy a packet)
Note: at Gigabit rate, gtxclk signal is provided to PHY, and TXD, TXEN and txer signals are synchronized with clock signals at this time. Otherwise, at the rate of 10 / 100M, PHY provides txclk clock signal, and other signals are synchronized with this signal. Its working frequency is 25MHz (100m network) or 2.5MHz (10m network).
RXCLK — receive clock signal (extracted from the received data, so it is not associated with gtxclk)
[7.. 0] – receive data
Rxdv — effective indication of received data
Rxer — receive data error indication
Col — conflict detection (half duplex only)
MDC — configure interface clock
MDIO — configure interface I / O
The management configuration interface controls the characteristics of phy. The interface has 32 register addresses, each with 16 bits. The first 16 of them have been specified in “IEEE 802.32000-22.2.4 management functions”, and the rest are specified by each device.
RMII： Reduced Media Independant Interface
Simplify media independent interface
It is one of the standard Ethernet interfaces and has less I / O transmission than MII.
On RMII port and MII port
RMII port uses two wires to transmit data,
The MII port uses four wires to transmit data,
Gmii uses eight wires to transmit data.
MII / RMII is just a kind of interface. For 10m line speed, the speed of MII is 2.5m, while RMII is 5m; For 100m line speed, the speed of MII is 25m and RMII is 50m.
MII / RMII is used to transmit Ethernet packets. The interface of MII / RMII is 4 / 2bit. In phy of Ethernet, serial to parallel conversion, encoding and decoding are required to transmit on twisted pair and optical fiber. Its frame format follows IEEE 802.3 (10m) / IEEE 802.3u (100m) / IEEE 802.1Q (VLAN).
The format of Ethernet frame is: preamble + start bit + destination MAC address + source MAC address + type / length + data + padding (optional) + 32bitcrc
If there is a VLAN, add a 2-byte VLAN tag after the type / length, where 12bit represents the VLAN ID and 4bit represents the priority of the data!