Anyone involved in the design of high-speed data capture using FPGA may have heard of the fashionable term of the new JEDEC standard: jesd204b. Recently, many engineers contacted Ti and asked for information about jesd204b interface, including how it works with FPGA and how to make its design easier to implement. So, what is jesd204b? This paper will discuss the development process of jesd204b standard and its significance to system design engineers.
What led to the emergence of jesd204b standard?
About a decade ago, designers of high-speed data converters shifted from using traditional single ended CMOS interface to using differential LVDS interface, because the latter realized higher data rate（ The CMOS interface rate is limited to about 200Mbps.) LVDS interface also improves the noise coupling between signal line and power supply. The disadvantage of this interface is higher power consumption at low sampling speed. This gives a reason for the existence of CMOS interface, which is still used today.
However, with the development of analog-to-digital converter (ADC), it requires faster sampling rate and higher channel density. The industry requires a faster and more efficient digital interface than parallel LVDS. In order to overcome this challenge, JEDEC developed and approved a real serial interface (called jesd204) in April 2006. The jesd204 interface is defined as a single channel, high-speed serial link that connects single or multiple data converters to digital logic devices using data rates up to 3.125 Gbps. It needs to send a common frame clock to the converter and FPGA to synchronize the frames.
Since only one channel and one serial link are supported, jesd204 is soon considered not as effective as previously hoped. Therefore, in April 2008, the standard was revised to jesd204a. Jesd204a extends support for multiple aligned channels and multipoint links, but the maximum speed is still limited to 3.125 Gbps. This became the driving force for the customization of jesd204b standard in July 2011, which aims to overcome several different system design problems. In addition to increasing the supported data rate from 3.125 Gbps to 12.5 Gbps, it also greatly simplifies multi-channel synchronization by adding deterministic delay function.
What is the jesd204b standard?
Jesd204b supports the interface speed of up to 12.5 Gbps, uses the device clock instead of the previous frame clock, and has three different subclasses. In addition to high speed, subclass 0 is downward compatible with jesd204a, but it does not support deterministic delay. In addition, the sync signal has special error reporting timing requirements (see Figure 1). Subclass 1 uses the synchronization signal sysref to initiate and align local multi frame clocks between devices (see Fig. 2). It synchronizes data transmission and realizes known and deterministic delay between digital links. Subclass 2 uses the sync signal for the same purpose (see Figure 3). Due to sync timing constraints, subclass 2 is usually used for data rates below 500 MSPs. In order to achieve speeds above 500 MSPs, subclass 1 with an external sysref clock is often preferred.
The receiver conforming to jesd204b standard has an elastic buffer to compensate for the skew between serializer / deserializer (SerDes) channels, which simplifies the circuit board layout. The elastic buffer will store data until the data of the slowest channel arrives. After that, the data of all channels are released at the same time for digital processing. This skew control is possible because the data clock is embedded in the serial data stream.
Why focus on the jesd204b interface?
Because the jesd204b standard data converter uses a higher rate than previous interfaces to serialize and send output data, the number of pins required on the data converter, processor or FPGA is greatly reduced, resulting in smaller package size and lower cost. However, the biggest benefit of reducing the number of pins is that the layout of printed circuit board (PCB) is simpler and wiring is easier, because there are fewer channels on the circuit board.
By reducing the need for skew management, layout and cabling are further simplified. By embedding the data clock in the data stream and the existence of elastic buffer in the receiver, the need to reduce skew management becomes a reality. Therefore, there is no need to route meandering to match the length. The jesd204b standard also allows longer transmission distances. The reduction of skew requirements allows the logic device to be far away from the data converter, so as to avoid the impact on sensitive analog components.
In addition, the jesd204b interface can adapt to different data converter resolutions. In this way, the transceiver / receiver (TX / Rx) board (logic device) can be used for future ADC and digital to analog converter (DAC) without physical redesign.
Does this mean the end of the LVDS interface?
CMOS interface reduces the power consumption of data converter through low data rate, while jesd204b interface has more advantages than traditional LVDS interface. So, does the LVDS interface still have a chance to survive?
The answer is yes. Although the jesd204b standard simplifies multi-channel synchronization through deterministic delay, some applications require minimum delay (ideally no delay). These applications (such as radar and other aviation applications) need to respond immediately to a certain action or detection behavior. All potential delays must be minimized. For these applications, LVDS interface should be considered because the data serialization delay of jesd204b standard data converter is ignored.
This paper discusses the development process of JEDEC jesd204b standard, and explains many benefits of using this interface, including higher data rate, simpler PCB layout, smaller package size and lower cost. We hope that readers can now better understand the jesd204b standard system.