With the deepening of current application technology, CF card (compact flsah card) is widely used in embedded products because of its advantages such as low price, large storage capacity, small volume and good compatibility. However, the existing CF card interface circuit has the disadvantages of complex interface and low stability, which can not meet the needs of customers. By deeply studying the working principles of external bus interface (EBI), CF card and CPLD of ARM processor AT91RM9200, it is proposed to use CPLD to improve CF card interface circuit to solve the shortcomings of existing interface circuits.
1 device introduction
1.1 external bus interface
The system uses AT91RM9200 with ARM920T as the core as the microprocessor. It is a system completely built around ARM920T thumb processor. It has rich system and application peripherals and standard interfaces, including a high-speed on-chip SRAM working area and a low latency external bus interface (EBI) to complete the seamless connection between the off-chip storage area and the internal memory mapping peripherals required by the application. The external bus interface structure is shown in Figure 1.
EBI supports CF card and SmartMedia protocol through integrated circuits, which greatly reduces the demand for external components. In addition, EBI can handle data transmission of up to 8 peripherals, each of which is allocated 8 address spaces defined in the built-in storage controller. Data is transmitted through 16 bit or 32-bit data bus. The address bus is up to 26 bits. Eight chip selection ports (NCS [7:0]) and multiple control pins multiplexed between different external storage controllers are multiplexed.
1.2 CF card
CF card (compact flash card) is a memory card using flash memory technology. It has the advantages of small volume, low price, strong compatibility and large storage capacity. The CF card supports three interface modes: pccard memory mode, PC card I / O mode and true idemode. Because true ide mode is not often used, the interface circuit is designed with PC card memory mode and PC card I / O mode.
CPLD (complex programmable logic device) is a more complex logic element  than PLD. It is a digital integrated circuit in which users construct logic functions according to their own needs. The basic design method is to generate the corresponding target file with the help of the integrated development software platform, schematic diagram, hardware description language and other methods, and transfer the code to the target chip through the download cable (“in system” programming), so as to realize the designed digital system.
The CPLD used in this paper is epm7128sql100-10 of max7000s series of Altera company. It has 84 pins, of which 5 are used for ISP (in system programmable) download, which can be easily programmed “in the system”. Epm7128sql100-10 supports voltage operation, and can be simulated, synthesized and downloaded conveniently by using Quartus II, the fourth generation development platform of Altera company.
2 hardware interface circuit design
The circuit diagram of the hardware interface circuit is shown in Figure 2. In this circuit, CPLD is used to realize the logic functions of some logic devices such as bidirectional buffer and NAND gate in the general CF card interface circuit, which makes the interface circuit simpler, stable and high-speed, and different functions can be realized by modifying the program on site.
In CF card_ CD1、_ CD2 is the status detection signal of whether the CF card is installed or not, which is grounded in the CF card. When the CF card is not installed, it is in the circuit_ CD1、_ CD2 pulls its output to high level by pull-up resistor; When the CF card is installed_ CD1、_ CD2 is grounded by the CF card and the output is low level_ CD1、_ CD2 is equivalent to the main switch of CF card. In the actual interface circuit_ CD1、_ CD2 shall be connected with a pull-up resistance of 10 K Ω.
Programming cs4a of the chip selection task register to 1 enables the multiplexing pins ncs4 / CFCs, ncs5 / cfce1 and ncs6 / cfce2 of EBI to be CompactFlash signals CFCs, cfce1 and cfce2, and enables noe / NRD / cfoe, nwr0 / new / cfwe, nwr1 / NBS1 / cfior, nwr3 / nbs3 / cfiow and a25 / cfrnw to be compact flash signals cfoe, cfwe, cfior, cfiow and cfrnw. In this way, the external CF card can be accessed by accessing the address space reserved for ncs4. In the address space of ncs4, the current transmission address is used to distinguish the I / O mode, and the general storage mode is the flag storage mode. A23 of the transmission address bus is used as I / O mode selection. In this paper, A22 / reg is used to separate general storage mode and flag storage mode.
In I / O mode, the logic of CompactFlash drives the read and write signals of SMC on cfior and cfiow signals. At this time, cfoe and cfwe signals fail. Similarly, SMC on cfoe and cfwe signals is driven in general storage mode and flag storage mode, and cfior and cfiow signals fail. The logic is shown in Figure 3.
Cfoe and cfwe are connected through CPLD and OE and we of CF card, which is the read-write enable of CF card in memory mode.
Cfioe and cfiow are enabled by I / O mode. Except for the enable signal, other signals are the same for both modes.
Cfce1 and cfce2 signals enable the data bus of CF card to be accessed from up or down. See Table 1 for specific information. Odd byte access can only be performed when the SMC on the ncs4 pin is configured to drive 8-bit memory, and the chip selection register in the ncs4 address space must be set as shown in Table 1.
_ CD1、_ CD2 is a low level, the lower 11 bits a [10:0] of the address bus of the CPU are connected to the address bus a [10:0] of the CF card, and the lower 16 bits d [15:0] of the data bus of the CPU are connected to the address bus d [15:0] of the CF card. A25 / cfrnw signal of CPU is the direction of data flow, and ncs4 / CFCs signal is the transmission enable of data bus. See Table 2 for details.
CPU is a high-speed device and CF card is a low-speed device. When CPU transmits data to CF card, data will be lost due to slow reception speed. So you need to use_ Wait signal to delay the transmission of CPU, so as to match the transmission timing of CPU with the reception timing of CF card and make the data transmission correct. Design of CF card in actual circuit_ The wait signal controls the nwait signal of the CPU through the CPLD_ Wait shall be connected with a pull-up resistor of 10 K Ω. RDY / BSY is the working status signal of the CF card. When RDY / BSY is 1, the CF card is ready to receive new data; When RDY / BSY is 0, the CF card is receiving data, and this signal should also be connected to a 10 K Ω pull-up resistor. The reset reset signal of CF card is also generated after the reset nreset signal of the system is inverted in CPLD to keep synchronization with the reset signal of the system.
3 CPLD program development
CPLD program is written in Verilog HDL language under Quartus II. After compiling, the program is downloaded to CPLD for solidification. Connect the circuit board and CF card, and read and write the data to the CF card. The test results show that the data transmission is correct and the transmission rate is higher.
This paper focuses on how to use CPLD to connect arm based embedded system with CF card. The CPLD not only simplifies the interface circuit and makes it suitable for field programming, but also the improved interface circuit is suitable for generating various complex combinational logic and sequential logic. The correctness of this storage technology has been verified on the circuit board. It provides an effective solution for CF card storage of arm based embedded system.
Source: China Electronics Network