ARM processor is widely used in embedded system design with low power consumption and energy saving. It is very suitable for the field of mobile communication. Consumer electronic products, such as portable devices (PDAs, mobile phones, multimedia players, handheld video games, and computers), computer peripherals (hard disks, desktop routers), and even military facilities such as missile borne computers.

Boot architecture is the key technology of embedded system. Mastering the startup architecture is of great significance to understand the operation principle of embedded system. When the embedded system is started, there are two main architectures: the boot code, the operation of the operating system and the loading of applications. One is the architecture directly started from NOR flash, and the other is the architecture directly started from NAND flash.

It should be noted that there are many situations during the boot process of embedded system. For example, the boot code bootrom of VxWorks can be divided into compressed and non compressed, resident and non resident modes, and the operating system itself is mostly stored in the form of compressed image. Therefore, the boot code needs to be processed according to different situations during execution and loading.

What is the architecture process of embedded arm

1 start from NOR Flash

NOR flash has the characteristics of on-chip execution (XIP, execute in place). It is often used as the first choice for storing startup code in embedded systems. The architecture launched from NOR flash can be subdivided into the startup architecture using only nor flash and the startup architecture using norflash and NAND flash together. Figure 5 shows the schematic block diagram of the two startup architectures.

1.1 use nor flash alone

In this architecture, boot code, operating system and application code coexist in the same nor flash. After the system is powered on, the boot code is first executed in NOR flash, and then the operating system and application code are loaded into higher speed SDRAM for operation. Another feasible architecture is to execute boot code and operating system in NOR flash, and only load application code into SDRAM for execution.

The architecture makes full use of the characteristics of execution in NOR flash chip, which can effectively improve the system performance. The disadvantage is that with the increase of the capacity of the operating system and application code, it needs a larger capacity and expensive nor flash to support it.

1.2 nor flash and NAND flash are used together

The separate use of NOR flash will increase the cost investment of products for applications with a large amount of code. A new way to improve is to adopt the architecture of the combination of NOR flash and NAND flash. A NAND flash is added to the architecture. The startup code and operating system are stored in NOR Flash (2m or 4m) (the operating system can be stored in NOR flash or NAND flash according to the size of the code), while the application code is stored in NAND flash, and the NAND flash capacity can be changed accordingly according to the size of the stored application code.

After the system is powered on, the boot code is directly executed in NOR flash, and the operating system and application code in NAND flash are loaded into higher speed SDRAM for execution. You can also execute the boot code and operating system in NOR flash, and only load the application code in NAND flash into SDRAM for execution. This architecture is one of the most widely used startup architectures in embedded systems.

1.3 starting from NAND flash

Some processors, such as the ARM920T series processor S3C2410 of SamSung company, support the mode of starting from nandflash. Its working principle is to load the first 4KB code stored in nandflash into an address called steppingstone (bootsram), and then start executing the boot code to complete the loading of the operating system and applications. This method requires a NAND controller inside the processor, and also provides a certain size of additional SRAM space. It has certain application limitations and is rarely used in actual development.

Source: China Electronics Network

Leave a Reply

Your email address will not be published. Required fields are marked *