As the data transmission rate is getting higher and higher, the data transmission interfaces in the computer system are basically serialized. External buses such as USB, PCIe, SATA, DP, etc. squeeze the parallel bus to only the memory bus. The last fortress. Of course, even the stubborn DDR at the end of the parallel transmission bus is constantly absorbing the technology on SERDES to improve itself, especially the equalizer (Equalization, EQ) technology. In the DDR5 standard, DRAM will be designated to cover DFE (Decision Feedback Equalization) ability.

As signal rates increase, several factors limit the continued increase in the effective data window width in a system synchronous interface approach.

The propagation delay of the clock to the two chips is not equal (clock skew)

The propagation delay of each bit of parallel data is not equal (data skew)

The propagation delay of the clock is inconsistent with the propagation delay of the data (skew between data and clock)

There are two ways to increase the transmission bandwidth of the interface, one is to increase the clock frequency, and the other is to increase the data bit width. So is it possible to increase the bit width of the data without limit? This involves another very important problem – Synchronous Switching Noise (SSN). With the increase of the data bit width, SSN becomes the main bottleneck for improving the transmission bandwidth.

Due to the non-ideal characteristics of the channel, the signal is transmitted from Tx to Rx through the FR4 PCB board. There will be signal insertion loss, return loss, near/far-end crosstalk in the middle, and if the frequency continues to increase, the signal will be seriously distorted, which requires equalization. and data clock phase detection and other technologies, which is the technology used by SerDes.

Difference Between Single-Ended and Differential Signaling

A single-ended signal uses one trace to transmit a signal, and the signal is determined by the level relative to the ground reference plane (0V GND) to determine the logic “L” and logic “H”, such as a TTL interface or a CMOS interface, is a single-ended signal .

As the rate increases, the rising/falling edge of the single-ended signal also becomes steeper, so the output switching noise can cause overshoot and undershoot of the signal, and when multiple signals are converted at the same time, the ground bounce (ground bounce) is also considered. At the same time, the single-ended signal uses the reference ground plane as the signal return path, which also brings challenges to the layout, and the reflection effect caused by the impedance mismatch of the transmission line will become very serious.

differential signal

Differential signal is different from single-ended signal. One signal line transmits signal and then refers to GND as a reference for high (H) and low (L) logic levels and serves as a mirror flow path. Differential transmission transmits signals on both transmission lines. , the amplitudes of the two signals are equal, the phase difference is 180 degrees, and the polarities are opposite, and they are coupled to each other.

Advantages of Differential Signaling

The first benefit of differential signaling is that small signals can be easily identified because you are controlling the “reference” voltage. In a single-ended signal transmission system with reference ground as a “0 V” reference, the exact value of the measured signal depends on the consistency of “0 V” within the system. The further apart the signal source and signal receiver are, the more likely it is that there will be differences between their local ground voltage values. The signal value recovered from the differential signal is largely independent of the exact value of “ground”, but within a certain range.

The second major benefit of differential signaling is that it is highly immune to external electromagnetic interference (EMI). An aggressor affects each end of a differential signal pair almost equally. Since the difference in voltage determines the value of the signal, this will disregard any identical interference present on both conductors. In addition to being less sensitive to interference, differential signals generate less EMI than single-ended signals.

A third benefit offered by differential signaling is the ability to handle “bipolar signaling” with ease and precision in a single-supply system. To handle a single-ended, single-supply system with bipolar signals, we must create a virtual ground at some arbitrary voltage (usually the midpoint) between ground and the power rail. A positive signal is represented by a voltage higher than the virtual ground, and a negative signal is represented by a voltage lower than the virtual ground. Next, the virtual ground must be properly distributed throughout the system. For differential signals, there is no need for such a virtual ground, which allows us to process and propagate bipolar signals with a high degree of fidelity without relying on the stability of the virtual ground.

With the development of integrated circuits and the requirement for higher data rates, low-voltage power supply has become an urgent need. Reducing the supply voltage not only reduces the power consumption of high-density integrated circuits, but also reduces the heat dissipation inside the chip, which helps to improve the integration level. An excellent example of reducing supply voltage and logic voltage swing is Low Voltage Differential Signaling LVDS.

Low Voltage Differential Signaling (LVDS) is a communication standard for high-speed point-to-point applications. Multipoint LVDS (M-LVDS) is a similar standard for multipoint applications. Both LVDS and M-LVDS use differential signaling, a two-wire communication method where the receiver detects data based on the voltage difference between two complementary electrical signals. This greatly improves noise immunity and minimizes noise emissions.

LVDS is a low-power logic used to replace Emitter Coupled Logic (ECL) or Positive Emitter Coupled Logic (PECL). The main standard for LVDS is TIA/EIA-644. Another standard is sometimes used for LVDS, namely IEEE 1596.3—SCI (Extensible Conformance Interface). LVDS is widely used for high-speed backplanes, cable and board-to-board data transfer and clock distribution, and communication links within a single PCB.

The advantages of LVDS include

Communication speed up to 1 Gbps or more

lower electromagnetic radiation

higher noise immunity

low power operation

Common Mode Range Allows Up to ±1 Ground Offset Difference


Standard TIA/EIA-899 for Multipoint Low Voltage Differential Signaling (M-LVDS) extends LVDS to solve problems in multipoint applications. Compared to TIA/EIA-485 (RS-485) or Controller Area Network (CAN), M-LVDS enables higher speed communication links with lower power consumption.

Additional features of M-LVDS over LVDS include

Higher driver output strength

Transition time controllable

Wider common mode range

Fail-safe receiver option for bus idle conditions

Why use LVDS or M-LVDS?

Figure 1 compares LVDS and M-LVDS with other multipoint and point-to-point protocols. Both standards have low power requirements. LVDS and M-LVDS feature differential signaling with low differential voltage swings. Compared to LVDS, M-LVDS specifies a higher differential output voltage in order to allow higher loads from a multidrop bus.

Both protocols are designed for high-speed communication. Typical applications use PCB traces or short wire/backplane links. The common mode range of LVDS is designed for these applications. Compared to LVDS, M-LVDS extends its common-mode range, allowing for additional noise in multipoint topologies.

LVDS/M-LVDS Application Considerations

Bus Types and Topologies

Clock Distribution Application

Characteristics of LVDS/M-LVDS Signals

Termination and PCB Layout

Jitter and Skew

Data encoding and synchronization


Reviewing Editor: Liu Qing

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