What is ddr5?

Open Baidu Encyclopedia, you will find that the description of ddr5 is very “crude”: “ddr5 is a computer memory specification”. This definition is OK, but it is not specific. Let’s take a closer look at it.

Ddr5 is the abbreviation of the fifth generation DDR SDRAM. DDR SDRAM is the abbreviation of double data rate SDRAM in English. It is translated into double rate SDRAM in Chinese. SDRAM is the abbreviation of synchronous dynamic random access memory, which is translated into synchronous dynamic random access memory. The synchronization object is the system clock frequency. Therefore, together, ddr5 means the fifth generation of double rate synchronous dynamic random access memory.

Source: Andy lock

It is not difficult to find that ddr5 is related to SDRAM literally. It is true that ddr5 is the fifth generation descendant of the improved version of SDRAM, and DDR functions as a temporary storage CPU Besides computing data, it also undertakes the mission of exchanging data with external memory such as hard disk. Therefore, it is not only necessary to meet the requirements of high-speed read-write, but also need to have the function of unlimited read-write. Of course, infinity is a theoretical value, limited by the influence of material and other factors, its life is usually more than ten years.

Development of SDRAM Technology

Before we talk about the history of SDRAM, we should popularize a concept of classification. From ram, RAM (random access memory) can be divided into two categories, one is dynamic RAM (DRAM), the other is static RAM (SRAM). DRAM is widely used in computer memory because of its simple structure, high integration, low power consumption and low manufacturing cost.

Similarly, DRAM can be divided into synchronous dynamic random access memory (SDRAM) and asynchronous dynamic random access memory (EDO DRAM) according to whether it is synchronized with the system clock.

In fact, before EDO DRAM, there was a “new form” of 486’s which was better than DRAM. Now it has been out of people’s view. It is fast page mode DRAM (FPM DRAM). The configuration is basically 30 lines / 72 lines, 5 V voltage, 32 bit bandwidth, and 60 NS basic speed. The typical timing is 6-3-3-3.

According to logic, the next thing I want to talk about is EDO DRAM. Do you remember the 586 computer that appeared in the 1990s? It was later called “Pentium”. At that time, the 8m memory was equipped with 72 line EDO DRAM, and the screen mosaic was so clearly visible. However, it is not without advantages. Compared with FPM DRAM, the performance of EDO DRAM is improved by 20% ~ 40%, which is due to its working mechanism, that is, when one set of data is output, the next group of data is preprocessed, which is the so-called preprocessing mechanism.

Later, there was SDRAM. Compared with the previous products, there was a qualitative leap in size and frequency, and the history of SDRAM was opened. By the beginning of 2020, SDRAM has experienced five main development stages: SDRAM, DDR, DDR2, DDR3, DDR4 and ddr5. At present, DDR4 is still widely used in the market. With the advent of a small number of samples, the final international standard of ddr5 is still under further development.

To a large extent, the development of memory has been bundled with CPU processors. Let’s take a look at it from generation to generation

SDRAM

Source: Sohu

With the introduction of Intel Celeron processor, amd K6 processor and related motherboard chipset, the performance of EDO DRAM has been unable to meet its requirements. Due to the synchronization of input and output signals and the convenience of 64bit bus width corresponding to the processor’s data bus width, SDRAM quickly replaced EDO DRAM. It is worth mentioning that in this iteration period, due to the frequency dispute between Intel and AMD, the external bus frequency of CPU processor rapidly increased from 100MHz to 133MHz, and the memory specification also developed from pc66 to PC100, PCII, PC133 and the less successful PC600, PC700 and pc800.

DDR

Source: ssyer

In 2000, the speed of DDR SDRAM (hereinafter referred to as “DDR”) was twice as fast as SDRAM, that is, double rate SDRAM. From this, the name of DDR was derived. Why can DDR achieve double rate? This is because the DDR adopts DLL delay lock loop technology and a data filtering signal, so that the DDR controller can carry out effective and accurate data positioning. In short, DDR can read data on both the rising and falling edges of the clock, so it can work at double rate. In addition, DDR uses SSTL2 standard 2, 5V voltage, lower than SDRAM LVTTL standard of 3.3V voltage, so the power consumption is lower.

Of course, in addition to technology, standardization comes first. During this period, the memory specification developed from PC133 to pc266, ddr333, DDR400 and ddr533 for overclocking.

DDR2

Source: pconline

With the continuous improvement of CPU front-end bus bandwidth and the emergence of high-speed local bus, DDR performance has become a throat locking technology that restricts the performance of the processor. Therefore, in 2003, Intel announced the development plan of DDR2 SDRAM (hereinafter referred to as “DDR2”).

Compared with DDR, the biggest highlight of DDR2 is the reduction of power consumption, which is due to the decrease of working voltage, that is, from 2.5V to 1.8V, and the working frequency is increased. How much has it been improved? The working frequency of DDR2 is about twice that of DDR, because the pre read capacity of DDR2 is 4 bit, while the memory pre reading capacity of DDR is 2 bit, that is to say, 2 times. This makes DDR2 break through the 400 MHz limit of DDR memory. Secondly, DDR2 adopts the mechanism of different internal and external clocks. Specifically, the internal clock is half of the external clock, while the internal and external clocks of DDR2 are the same. This also explains the reason that DDR2 Memory has different clock frequencies of 400, 533, 667mhz, and the capacity density is 512MB. Finally, DDR2 abandons TSOP, opens the door of memory FBGA package, reduces parasitic capacitance and impedance matching problems, and increases stability.

DDR3

Source: photo web

In 2007, JEDEC Association officially launched DDR3 SDRAM (hereinafter referred to as “DDR3”) specification, DDR3 began to go to the stage.

Compared with DDR2, thanks to the advanced production process, the working voltage of DDR3 is reduced from 1.8V to 1.5V and 1.35v (ddr3l), which further reduces power consumption and heat generation. It also adopts functions such as automatic self refresh and local self refresh according to temperature, which can make up for the long delay time of DDR3 to a certain extent. At the same time, the speed of DDR3 starts from 800MHz and reaches 1600MHZ, which is almost twice the speed of DDR2. How did this happen? Because DDR3 can output 8 bit data in one clock cycle, while DDR2 is 4 bit, the data transmission amount per unit time is twice that of DDR2. In addition, the pre read ability of DDR3 is 8 bit, which is twice as much as DDR2, so that the kernel frequency of DDR3 is only 1 / 8 of the external frequency.

DDR4

Source: photo web

At the end of 2014, DDR4 memory products with a take-off frequency of 2133mhz came into the market, which marked the arrival of DDR4 era. Up to today, DDR4 still occupies the mainstream position in the market.

Compared with DDR3, the working voltage of DDR4 is reduced from 1.5V to 1.2V and 1.05v (ddr4l), which means more power saving and less heat generation. In terms of speed, starting from 2133mhz, the highest speed can reach 4266mhz, nearly three times of DDR3. How is this achieved? First of all, we will talk about the transmission mechanism. In addition to supporting the traditional se signal, DDR4 also introduces the differential signal technology. In other words, this is the evolution to the two-way transmission mechanism stage. Secondly, DDR4 adopts the point-to-point design, which simplifies the design of memory module and makes it easier to realize high-frequency. Finally, DDR4 has introduced differential signal technology The three-dimensional stack packaging technology is used to increase the capacity of the unit chip. At the same time, the temperature compensation self refresh, temperature compensation automatic refresh and data bus inversion technology are also used, which has a good effect in reducing power consumption.

DDR5

Source: AnandTech

The nuclear war between Intel and AMD is becoming more and more fierce. Now the desktop computer starts to take off with 6 cores. It can be predicted that the performance of memory will become a new bottleneck again. Therefore, as early as 2017, JEDEC Association began to work with major s DRAM manufacturers to draft ddr5 standards. In 2018, it published the draft of ddr5 technical specifications. On February 19, 2019, JEDEC announced the updated standard of lpddr5, but no official version has been released. Therefore, “why is ddr5 not popular?” I’ll explain this in the following chapters. Let’s look at the difference between ddr5 and ddr5?

What are the new technical features of ddr5?

Ddr5 SDRAM (hereinafter referred to as “ddr5”) is the most obvious progress compared with DDR4.

Photo source: Meguiar

Representation

According to JEDEC’s draft, in terms of capacity, the capacity of a single ddr5 is from 8GB to 64GB; in terms of speed, ddr5 jumps from 3.2gbps to 6.6gbps, with the highest scalability of 8.4gbps; the prefetch capacity increases from 8N of DDR4 to 16N, and the length of burst data changes to 16; in terms of power consumption, the working voltage of ddr5 is reduced from 1.2V of DDR4 to 1.1V; in addition, in terms of function, ddr5 has the function of reducing the operating voltage of ddr5 from 1.2V to 1.1V In addition to following the basic functions of activation, read-write, precharge, refresh, self refresh, power saving mode, ZQ calibration and other basic functions, many new functions, or new features, are also added, which is what this chapter focuses on. I don’t say much, but I’ll take it with you

Technical analysis

Source: ssyer

Command and address signals share the CA bus

Ddr5 is the first time in the history of memory technology that command and address signals are combined into a CA bus. Compared with the independent characteristics of command and address signal pins in DDR4 and previous memory products, ddr5 has a great difference in parsing methods. Specifically, when DDR4 and previous memory products are working, the DRAM command receiver will sample all the command signals to analyze the current command and obtain the address information according to the demand under the premise that the chip selection signal is valid. When the rising edge comes, the DRAM command receiver will sample all the command signals to obtain the address information, which means that all operations can be completed in one clock cycle. Because ddr5 uses CA bus, many commands need two clock cycles to complete. When the first rising edge comes, the CA signal is sampled to analyze the command, and then another CA signal is sampled to resolve the address when the second rising edge comes.

On the surface, it seems that this wave of operation has increased the complexity of the analysis. In fact, it is also a helpless move. With the increase of capacity and speed, the number of address signals will also increase. This is not difficult to understand, just as there are more workers, there are always more dormitories to be provided. Of course, more than that, you also need to provide workers with more life security, which is mapped into the memory. Considering the requirements of high-speed transmission, the number of golden fingers in ddr5 memory module will increase with the increase of VDD pins to meet the requirements of the shortest current return path. Let’s imagine, as soon as the number of golden fingers increases, will the size increase? This violates the trend theorem of miniaturization of electronic products, so CA bus is chosen. As a result, the original demand for more than 300 gold finger pins was reduced to 14 CA pins, and the number of pins and solder balls could be kept consistent with DDR4 arbitrarily.

2n mode

What is 2n mode? Don’t think it’s complicated. In fact, in order to match the command input mode which needs two consecutive cycles, the 2n mode control bit is used to determine the specific CA bus sampling interval.

Adding decision feedback equalizer DFE

Why introduce DFE into DQ receiver? We should bear in mind that only when there is a problem will we have to solve the problem, and in the process of solving the problem, we often need to make some changes to increase or decrease. This is no exception. When the data rate exceeds 3.2gbps, ISI will increase, and the decrease of signal-to-noise ratio may lead to complete closure of eye diagram at DRAM solder ball. The highest data rate of ddr5 can reach 8.4gbps, so we must take some measures to solve this problem. The current way is to add some equalizer to improve the eye diagram, such as the four tap DFE composed of one gain amplifier, one DFE adder, four DQ slicers and one parameter multiplier proposed in ddr5 specification draft.

low power consumption

Power consumption has always been the focus of memory performance. Who wants to pay for a “hot fast”. For ddr5, it follows many features of lpddr4, such as expanding mode registers to 256, adding mode register read command MRR and multi-purpose command MPC, so as to realize interface initialization, training (focus: read training, read leader training, CA training, video selection training, writing training and vrefca training), periodic calibration and other functions.

Loopback mode

It is also the high-speed rate that leads to the birth of loopback mode. Why not talk about it before power consumption? This is because the loopback mode is mainly used in the test, which is used to test the bit error rate, so as to judge the performance of the receiver. Those who have studied software know that we usually use the write read method to test the receiver. However, when the speed is as high as 8.4gbps, the internal space of DRAM will not be enough and the test time will be very long. In order to improve the stability and efficiency of the test, the technician proposes a loopback mode, which allows ddr5 to directly return the test data sent by the memory controller or the driver of the test equipment to its receiver, eliminating the command of reading and writing alone. However, all things have to pay a price. Adding lbdqs (single ended DQS signal), LBDQ (DQ signal) pins and mode register are what ddr5 needs to pay. The former is used to return the received data to the opposite end in loopback mode, and the latter is used to control the data received by the corresponding pin of ddr5 to the sender.

other

Due to the space, all the new technical features of ddr5 are not listed here, such as on-chip ECC, write mode command, DQS internal oscillator, etc. If you are interested, you can leave a message at the end of the article or inquire about JEDEC specification draft.

Ddr5 status and DRAM Market

Photo source: Meguiar

First of all, let’s answer “why is ddr5 still not popular?” To be honest, this problem is probably raised by users waiting for a new generation of ddr5, because they are worried about whether to wait for a new generation of ddr5 or to start a mature DDR4. However, from the point of view of the average life cycle of memory, this kind of sample test is successful and the mass production is just around the corner. After all, if we don’t build a complete production line of RAM in advance, which manufacturer can’t choose? It’s all money. Like Moore’s law, capitalists will maximize the profits of each generation of products before they enter the next level. Therefore, it is wise to follow the main core.

Secondly, from the perspective of total market volume, DRAM’s market seems to have an inflection point in the third quarter of 2019 after the memory market has been falling for a year. According to the Q3 report of DRAM exchange, a semiconductor research center under Jibang technology, although the memory price is still falling, and Q3 is still falling by nearly 20% on quarter, the output value of memory has reached $15.45 billion, an increase of 4.1% on a month on month basis. This has conveyed two news to us. On the one hand, due to the large supply of the market, the price has been continuously lowered; on the other hand, it also shows that in addition to the increase of stock preparation brought about by the Sino US trade war, the demand for memory in the smartphone and server market is increasing.

Source: trendforce

Since December 2019, due to the drop of inventory level of terminal ODM / OEM factory, mobile phone factory and system factory, the purchase volume of houses began to expand, and DRAM price rebounded. It is reported that the spot price of 8 GB DDR4 standard DRAM has risen to about $3.5, up more than 10% since January, while the spot price of 4GB DDR4 standard DRAM has risen to more than $2, with an increase of about 17% since January.

In terms of ddr5 market share, SK Hynix predicts that the sales volume of ddr5 modules will account for 25% of ram market in 2020 and 44% in 2021. However, some analysts said that although there are some ddr5 rdimm samples on the market, large-scale use will not be realized until the end of 2022 and early 2023.

Source: photo web

Finally, from the perspective of market distribution, manufacturers mainly include Samsung, SK Hynix, Mei Guang and South Asia technology, Hubang electronics, and Lijing technology, Taiwan, China. The Chinese mainland plate is relatively backward. But with the completion and commissioning of the first 300 millimeter wafer factory in Hefei, Changxin storage will produce the first generation 10nm technology level 8Gb DDR4 in China. Memory chips, from this Chinese mainland will soon bid farewell to the era of DRAM free memory factory, the wafer factory output is 20000 wafers per month, and the output will increase to 40000 Wafers / month in the second quarter of 2020, which will probably account for 3% of the global memory capacity.

From the memory design market point of view, China has also made a qualitative leap in the DDR4 era. The DDR4 full buffer “1 + 9” architecture of LanChi technology listed on the science and technology innovation board was finally adopted by JEDEC international standard. At the same time, when ddr5 is coming, LanChi technology has also made some achievements in the layout and development of ddr5 memory interface chips. According to its internal information, its new generation products can effectively support the requirements of ddr5, such as high speed and low power consumption. It is expected to complete the R & D and industrialization of the first generation ddr5 memory interface chip within three years.

Write it at the end

Said so much, as a hardware engineer, or from the perspective of the system to talk about the arrival of ddr5 a few ideas. For most hardware designers, we have been using DDR4 in recent years, so we have to worry about the upgrading of DDR, such as the selection of supporting system upgrade devices of ddr5, the upgrading of serial link filtering technology, the construction and Simulation of system prototype, the pressure of system cost, etc. However, I believe that my comrades in arms, like human flesh equalizers, can make the most appropriate choice on these key nodes, and then move on.

PS: to say more, at the present time of the epidemic, our generation needs to work hard, unite and wisdom, and walk out a “road of Chinese memory” when ddr5 comes.

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