Verilog HDL and VHDL are the two most commonly used hardware description languages, and they are also IEEE standard HDL languages.

Verilog HDL description:

Verilog HDL is a hardware description language, which is used to model digital systems from algorithm level, gate level to switch level. The complexity of the digital system object to be modeled can be between a simple gate and a complete electronic digital system. Digital systems can be described hierarchically and can be modeled explicitly in the same description.

Verilog HDL language has the following description capabilities: behavior characteristics of design, data flow characteristics of design, structure of design, delay and waveform generation mechanism including response monitoring and design verification. All of these use the same modeling language. In addition, Verilog HDL provides a programming language interface, through which the design can be accessed from outside during simulation and verification, including the specific control and operation of simulation.

Verilog HDL language not only defines syntax, but also defines clear simulation and simulation semantics for each syntax structure. Therefore, the model written in this language can be verified by Verilog simulator. Language inherits many operators and structures from C programming language. Verilog HDL provides extended modeling capabilities, many of which are initially difficult to understand. However, the core subset of Verilog HDL is very easy to learn and use, which is enough for most modeling applications. Of course, a complete hardware description language is enough to describe from the most complex chip to the complete electronic system.

VHDL description:

VHDL is a high-level language for circuit design. It appeared in the late 1980s. It was originally developed by the U.S. Department of defense to improve the reliability of design and reduce the development cycle. VHDL is mainly used to describe the structure, behavior, function and interface of digital system. In addition to many statements with hardware characteristics, the language form, description style and syntax of VHDL are very similar to general computer high-level languages.

VHDL translated into Chinese is the hardware description language of ultra high speed integrated circuit, which is mainly used in the design of digital circuit. Most of its applications in China are in the design of FPGA / CPLD / EPLD. Of course, in some powerful units, it is also used to design ASIC.

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