1、 Foreword

Whether it is FPGA application development or digital IC design, timing constraints and static timing analysis (STA) are very important design links. In FPGA design, sta can be performed after synthesis and implementation to check whether the design can meet the timing requirements. This paper describes the basic timing constraints and sta operation flow. The content mainly comes from the book vivado starts from here. I am just a knowledge porter.

2、 Timing constraints and Xdc scripts

The purpose of timing constraints is to tell the tool the current timing status, so that the tool can optimize the timing as much as possible and give a detailed analysis report. Generally, basic timing constraints are created after behavior simulation and before synthesis. Vivado uses Xdc scripts based on SDC to constrain in text form. The following discusses how to perform basic timing constraint related scripts.

1 the primary task of timing constraint is to create a master clock, which generates a clock for the clock pin to enter the clock signal or the high-speed transceiver. [create_clock]

create_ clock -name clk_ Name -period n-waveform {pos\u time neg\u time}[get\u ports port\u name] (the underlined part is optional)

Create two asynchronous master clocks:

create_clock -name clk_a -period 10 [get_ports clk_a]

create_clock -name clk_b -period 15 [get_ports clk_b]

set_clock_groups -asynchronous -group clk_a -group clk_b

When two master clocks are asynchronous, their generated clocks are also asynchronous:

set_clock_groups -asynchronous -group [get_clocks clk_a -include_generated_clocks]

-group [get_clocks clk_b -include_generated_clocks]

Differential clock only constrains P port:

create_clock -name clk -period 10 [get_ports clk_p]

High speed transceiver generates clock as master clock:

create_clock -name gt0_txclk -period 8 [get_pins GT0/…/TXOUTCLK]

There is a special case where a virtual clock is created without binding to a specific pin. This constraint is used to set the I / O delay. The scenario where the virtual clock needs to be created is that the data input to the FPGA generates clock sampling internally, such as serial port communication.

create_clock -name clk_v -period 5

2 after creating the master clock, you need to constrain the generation clock: [create\u generated\u clock]

There are two types of generation clocks. Vivado will automatically generate relevant constraints for the clock signals generated by dedicated clock units such as PLL MMCM. There is also a custom generated clock, which is generally obtained by logical frequency division.

The clock source is the clock port:

create_ generated_ clock -name clk_ div -source [get_ports clk] -divide_ By 2 [get_pins rega/q] means the clock signal CLK on the Q pin of the rega unit_ Div is the generation clock obtained by CLK through 2 frequency division.

Clock source is pin:

create_generated_clock -name clk_div -source [get_pins rega/C] -divide_by 2 [get_pins rega/Q]

In addition to using -divide_ by -multiply_ By indicates the frequency relationship between the master clock and the generated clock. It can also be expressed more accurately with -edges:

create_generated_clock -name clk_div -source [get_pins rega/C] -edges {1 3 5} [get_pins rega/Q]

Use -edge for phase shift relation_ Description of the shift command.

This constraint command is also commonly used to rename clockticks:

create_generated_clock -name clk_rename [get_pins clk_gen/…/CLKOUT0]

3 create a clock group: [set\u clock\u groups]

a. Asynchronous clock condition:

set_ clock_ groups -asynchronous -group clk_ a -group clk_ b clk_ A and CLK_ B is an asynchronous clock.

b. Physical mutual exclusion:

create_clock -name clk_a -period 10 [get_ports clk]

create_clock -name clk_b -period 8 [get_ports clk] -add

create_clock -name clk_c -period 5 [get_ports clk] -add

set_clock_groups -physically_exclusive -group clk_a -group clk_b -group clk_c

This case is only to observe whether the timing converges when the CLK pin clock signal cycle is 10ns, 8NS and 5ns respectively. Therefore, the three clocks do not physically exist at the same time.

c. Logical mutual exclusion:

set_clock_groups -logically_exclusive

-group [get_clocks -of [get_pins clk_core/…/CLKOUT0]] -group [get_clocks -of [get_pins clk_core/…/CLKOUT1]]

Clkout0 and clkout1 are sent to bufgmux, and then which one is selected as the working clock is determined according to the SEL signal. At this time, clkout0 and clkout1 exist in the circuit at the same time, but only one will be used as the working clock of subsequent circuits, so they are logically mutually exclusive.

Special usage: when there is only one asynchronous group, it indicates that the clocks in the reorganization are synchronous, but asynchronous with all other clocks.

4 set pseudo path: [set\u false\u path]

After setting the pseudo path, the timing analysis of the special path is no longer performed. Special paths such as test logic, cross clock domain path after adding synchronization circuit, etc. The two clock domains should be set to each other_ false:

set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]

set_false_path -from [get_clocks clk_b] -to [get_clocks clk_a]

5 common clock related commands:

report_ Clocks: view all clocks created

report_property [get_clocks ]: View clock CLK_ Attribute of name

report_ clock_ Network: view the generation relationship network of the clock

report_ clock_ Interaction: View clock interaction

The last one is very important. It is often used to check whether the path between asynchronous clock domains is secure. If there is an unsafe path, set it to asynchronous clock group or false after adding synchronization, handshake or FIFO_ path。


When you type this command, a clock interaction matrix is generated. The diagonal is the internal path of each clock, and other non black parts are the cross clock domain paths corresponding to two clocks. The red part is an unsafe path. If it is not handled, metastable state will be generated.

3、 View time series report (STA)

This section takes a project with many timing problems as an example to explain. After synthesis, you can open the timing summary to view the timing report.


After opening, the following interface appears:


Design timing summary is the timing overview, including maximum delay analysis, minimum delay analysis and pulse width. Where WNS or WHS is a negative number, indicating that the current design cannot meet the requirements of setup time or hold time, that is, the data cannot be stably sampled.

Information in clock summary and use report_ The clocks TCL script calls out similar information, including all created clockticks. The check timing section contains unconstrained parts. We can add necessary constraints based on the information in this section. Intra clock paths and inter clock paths describe the margin parameters of synchronous and asynchronous circuit timing paths respectively.

Click the value after WNS or WHS to directly find the path with the worst timing margin:


Double click anywhere on the path information line, and the interface will jump to the path details interface:


Among the four types of timing paths, except for the special case from FPGA input port to output port, other timing paths are composed of source clock path, data path and destination clock path. See the official document ug908 for detailed explanation of items in the above table

Reviewed by: Li Qian

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