What is Verilog HDL?

Verilog HDL (hardware description language) is a hardware description language, which can model digital systems at a variety of abstract design levels from algorithm level, gate level to switch level. It can describe the behavior characteristics, data flow characteristics, structure composition, time delay and waveform generation mechanism including response monitoring and design verification. In addition, Verilog provides a programming language interface through which users can access the design from the outside during simulation and verification, including the specific control and operation of simulation.

Verilog not only defines syntax, but also defines clear simulation and simulation semantics for each syntax structure. Therefore, the model written in this language can be verified by Verilog simulator. Verilog inherits a variety of operators and structures from C language, so they have many similarities in structure.

Verilog learning points

Verilog HDL is the language you use when developing FPGA and ASIC, which is the same as using C language when developing software.

Verilog is a way of thinking

Let’s talk about how to learn Verilog well. Some people say that learning Verilog is very difficult, which seems to be even more difficult than C language. It is true that there is some difficulty, but no language is more difficult to learn than other languages. When we first started learning C language, we also felt that C language was very difficult until we changed our way of thinking, learned the principle of microcomputer well, and could simulate the operation mode of CPU to think about problems. We will find that C language is not so difficult. Therefore, there is a process of transformation of thinking mode. This is the same for learning Verilog, but Verilog is lower than C language. We only master the thinking mode of CPU. We still need to learn another layer of “thinking mode of hardware circuit” to better master the hardware programming language.

Verilog design considerations

In the process of learning Verilog, some experiences are summarized. In order to ensure the comprehensiveness of Verilog HDL assignment statements, the following points should be paid attention to during modeling:

Do not use initialization statements;

Delay statements are not used;

Initial is not used.

Not used #10

Do not use statements with uncertain cycle times, such as: forever, while, etc;

It is strongly recommended to design the circuit in synchronous mode;

Try to use behavior statements to complete the design;

The always process block describes the combination logic, and all input signals shall be listed in the sensitive signal table;

The same variable cannot be assigned in more than one always procedure block. For the same assignment object, both blocking assignment and non blocking assignment cannot be used;

Except for the design of critical path, the method of calling gate level components to describe the design is generally not used. It is recommended to use behavior statements to complete the design;

All internal registers should be able to be reset;

User defined components (UDP components) cannot be integrated;

Always remember the timing problem in design;

At the beginning of a design, ground level or high-level reset, synchronous or asynchronous reset, rising edge or falling edge trigger and other problems shall be considered, and it shall be observed in all modules;

In different cases, if and case should be used. It is better to use less multi-layer nesting of if (one or two layers are more appropriate. When it is more than three layers, it is better to modify the writing method, because it can not only reduce area, but also obtain good timing);

The assignment of the same variable cannot be controlled by multiple clocks, nor by two different clock conditions (or different clock edges).

All internal registers should be able to be reset. When using FPGA to realize the design, the global reset end of the device should be used as the overall reset of the system as far as possible;

Be careful when locking a signal or bus. For the whole design, try to avoid using latch, because it is difficult to test in DFT;

Make sure that all signals are reset. During DFT, all flipflops are controllable;

Never read any internal memory (such as SRAM) before writing;

Data buffer is used when transmitting data from one clock to another. It works like a dual clock FIFO (asynchronous). Async SRAM can be used to build async FIFO;

For the description and modeling of temporal logic, non blocking assignment should be used as much as possible. For the description and modeling of combinatorial logic, either blocking assignment or non blocking assignment can be used. However, in the same process block, it is better not to use blocking assignment and non blocking assignment at the same time;

In VHDL, two-dimensional arrays can be used, which is very useful. In Verilog, it can only be used in the test module and cannot be integrated;

Comply with register in register out rules;

The DC integration tool of Synopsys is very stable, and no bugs will be generated from the integration tool;

Ensure that the FPGA version is similar to the ASIC version as much as possible, especially the SRAM type. If the version is consistent, it is ideal. However, in work, the FPGA version generally uses the SRAM provided by the FPGA, and the ASIC version generally uses the SRAM provided by the manufacturer;

If you do not intend to deduce a variable as a latch, you must explicitly assign a value to the variable in all conditional branches of an IF statement or a case statement.

Use BIST in embedded memory;

Avoid mixed use of triggers triggered by rising edge and falling edge;

Virtual cells and some correction circuits are necessary;

Some simple test circuits are also needed. There are often many test modules in a chip;

Do not use gated clock unless the power consumption is low. It is strongly recommended not to use gate clock in design;

Don’t rely on scripts to ensure design. However, some good constraints in the script can achieve better performance (such as forward adder);

If there is enough time, make a multi latch through the clock to replace MUX;

Do not use internal tri state. ASIC needs bus holder to handle internal tri state, such as IO cell;

Make pad insertion in top level;

Be careful when selecting pad (such as pulling capacity, Schmitt trigger, 5V withstand voltage, etc.), and select the appropriate IO cell;

Be careful of problems caused by clock deviation;

Do not try to generate a half cycle signal;

If there are many functions to be corrected, please do it one by one, correct a function and check a function;

It is a good habit to arrange the number of bits of each signal in a calculation equation, even if the synthesis tool can do it;

Do not use the divider provided by HDL;

Cut unnecessary clocks. It will cause a lot of trouble in design and layout. Most FPGAs have 1-4 special clock channels.


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