Just as rabbits tempt dogs to race, rabbits must run faster than dogs. The performance of the most stringent data acquisition system is naturally higher than that of civil analog-to-digital converter (ADC). These extremely strict requirements promote the development of IC manufacturers and their users, and there are many innovative methods of “enhancing performance” to meet the needs of high-end data acquisition systems.
One method is to greatly increase the sampling rate, reduce noise or expand the dynamic range by filling the “time slot” of the converter with multi-channel ADC. With the reduction of the cost, size and power consumption of a single ADC under a given bandwidth and resolution, and with the increasing application of multiple converters (usually packaged together), this method becomes more and more feasible.
This paper will discuss two multi-channel methods: signal averaging — ensuring that the sampling rate remains unchanged and increasing the resolution; Time interleaving – keep the resolution unchanged and improve the sampling rate. Products using these two methods have been born, such as ADI’s ad10678 (16 bit, 80 MSPs ADC) and ad12500 (12 bit, 500 MSPs ADC).
Signal to noise ratio (SNR, in DB) is a key performance index in imaging and radar applications. ADCs used in these systems may be affected by many external noise sources, including clock noise, power supply noise and coupled digital noise introduced by wiring. As long as the square root of the sum of squares (RSS) of uncorrelated noise sources is less than the inherent quantization noise of ADC, the output average will effectively reduce the overall background noise.
Systems that require higher SNR usually use digital post processors to sum the outputs of multiple ADC channels. The signals are added directly, while the noise from a separate ADC (assuming no correlation) is RSS summed, so the output sum improves the overall SNR. The sum of the four ADC outputs will increase 6 dB SNR, i.e. 1 LSB. AD6645 14 bit 80 MSPs ADC specifies that the significant bit (ENOB) is 12. Fig. 1 shows that the output sum of the four AD6645 increases 2-bit resolution and 1-bit performance.
The input of each ADC contains a signal term (VS) and a noise term (VN). The total voltage Vt obtained by summing the four noise voltages is equal to the linear sum of the four signal voltages plus the RSS value of the four noise voltages, namely:
Since VS1 = VS2 = vs3 = VS4, the equivalent signal is amplified by four times, while the noise (RMS value) of ADC is only amplified by two times, so that the signal-to-noise ratio is increased by two times, that is, 6.02 dB. Therefore, the 6.02 DB increment (∆ SNR) obtained by summing four signals improves the effective resolution by 1 bit. Because SNR (DB) = 6.02n + 1.76, n is the number of digits, so,
The SNR increment obtained by adding multiple ADC outputs is shown in Table 1. For simplicity, the addition of four ADCs is an obvious choice. Some important applications will also consider more ADC summation, but it should depend on other system index requirements (including cost) and available printed circuit board (PCB) size.
The ideal SNR of 14 bit ADC is (6.02 × 14） + 1.76 = 86.04 dB。 However, the typical value of SNR provided in the technical data of AD6645 is only 74 dB, so its ENOB is only 12 bit.
Therefore, the output summation of the four-way converter can compensate for the additional 1-bit resolution, and the original system level ENOB can reach 13 bit (80 dB).
Of course, such a system needs to pay some design efforts, as well as the cost of system prototype design, qualification and test development. However, the ad10678 integrates four AD6645, a clock distribution system, and a configured complex programmable logic device (CPLD) to provide high-speed addition. The ad10678 is now available at low cost and occupies 2.2 × The package with 2.8-inch PCB area fully meets the specified technical indicators through testing. The fast Fourier transform (FFT) results shown in Figure 2 demonstrate the excellent performance of the ADC, which can provide 80.22 dB SNR under the conditions of 80 MSPs clock and 10 MHz analog input.
In addition to improving SNR, this architecture also improves dc accuracy. The offset and gain error of the four ADCs are not related, so the same method as reducing noise is used to reduce the system offset and gain error. However, there is no improvement in linear error. In fact, spurious free dynamic range (SFDR) depends on the worst ADC.
However, this scheme needs to occupy a large PCB area and 4 times the power consumption, but compared with the output average scheme of single ADC working at 4 times the sampling rate, this method still has advantages. Although increasing the number of sampling points by increasing the sampling rate will also reduce the normal mode noise in the input signal. With the improvement of manufacturing process, the new design further reduces the core power consumption of ADC; In addition, the emergence of available 4-channel and 8-channel ADCs makes it easier to implement a multi ADC system and reduces the package size. For example, ad9259 4-channel 14 bit, 50 MSPs ADC uses 48 lead lfcsp (7 mm × 7 mm) package with a power consumption of only 100 MW per channel.
Although it is feasible to increase the specified SNR by increasing the input voltage, this will increase the design pressure of the drive amplifier and reduce the system SNR because the signal and noise are amplified together. Another subtle advantage of the summing architecture is that the full-scale analog input does not need to be larger than the input when using a single ADC.
Comparing the cost of hardware and software, the signal averaging method itself has advantages over digital filtering, but for the overall system to provide cost-effective hardware processing and software filtering, considering the required digital filtering, software often makes the work easier.
The time interleaving of M ADCs can increase the sampling rate to m times. By reasonably configuring the phase of each ADC clock signal, the maximum sampling rate of any standard ADC IC can be multiplied by the number of ADCs in the system. The appropriate clock phase required by each ADC can be calculated according to the following formula:
M represents the number of ADCs
M represents the serial number of specific ADC, i.e. 1 ≤ m ≤ M
For example, a 4-channel system composed of ad9444, 14 bit and 80 MSPs ADC will produce the effect of 14 bit and 320 MSPs when the clock phase of each channel increases appropriately at 90 ° (π / 2) intervals. Fig. 3 shows a basic block diagram of such a system. The time interleaving method of 12 bit integrated solution has been adopted in ad12400 / ad12500 series products. Fig. 4 shows a block diagram of ad12500, including all necessary functions of ADC, clock management, power supply and digital post-processing.
The most obvious advantage of increasing the sampling rate of ADC system is to increase the analog sampling bandwidth, also known as Nyquist band. Increasing Nyquist frequency band in digital instrument system can provide many benefits: digital oscilloscope can expand analog input bandwidth; Software defined radio system can increase the number of channels; Radar system can improve spatial resolution. Fig. 5 shows a simulation FFT diagram of a 14 bit, 320 MSPs ADC system sampling a 22 MHz frequency signal.
The FFT spectrum of the ADC system has a 160 MHz Nyquist band. For the convenience of discussion, the 160 MHz Nyquist bandwidth is divided into four independent 40 MHz bands, and each band represents the Nyquist band of a single ad9444 with a sampling rate of 80 MSPs. The 22 MHz fundamental frequency is located in band 1. It can be observed in Fig. 5 that in addition to the fundamental frequency, two types of non harmonic distortion components – offset spurious and mirror spurious can be observed. The position of distortion component caused by single frequency input signal can be determined by the following relationship:
The emergence of these distortion components is a major challenge related to time interleaving. They directly affect the gain, phase and offset matching errors between channels. In fact, the amplitude of these spurious signals is directly proportional to the error amplitude 1,2. For example, a gain error of 1% on one channel results in a mirror spurious amplitude of 52 DBC. When the system frequency planning involves the frequency band located in the distortion sideband, these stray signals will become a problem. In this case, the matching characteristics between channels must be carefully managed in the development process. If the system performance target is 10 bit ENOB and the image stray signal is the main factor, the gain matching error must be better than 0.1% and the phase matching error must be better than 0.07 ° (2PS @ 100 MHz)! In order to achieve this performance level, many different error sources must be reduced or eliminated from the perspective of implementation.
The printed line size of analog input and clock input of each ADC must match to ensure that the propagation delay is within the budget level. Although the function of the clock circuit is very simple, it will also introduce errors affecting the system performance. Compared with the existing ECL manufacturing processes, advanced processes, such as silicon germanium rsecl (low swing ECL) process, can provide great improvements in signal rise, fall and propagation delay. According to the input frequency, manual line length adjustment can also be adopted to overcome the aperture delay error.
Due to the difference between power performance levels, it is necessary to use a power supply with small allowable error, such as a linear regulator installed close to the ADC. In addition, the temperature related performance also needs to be strictly matched with the temperature characteristics of ADC through mechanical design. When selecting ADC, it is also necessary to consider the matching of one or all of the following indicators: gain, offset, aperture delay and input capacitance. Obviously, it is very difficult and expensive to select four independent ADC with the allowable error of all key performance indicators to strictly match! The increased complexity and risk of system design development and component costs must be carefully weighed.
The analog adjustment processing scheme can match with the ADC channel in the time interleaving system under very narrow working conditions. However, the digital post-processing method can achieve strict channel matching under a wide range of working conditions. High speed and configurable digital platforms, such as field programmable gate array (FPGA), provide convenient tools for integrating advanced post-processing methods, such as AFB advanced filter banks.
Ad12400 12 bit, 400 MSPs ADC contains two High-Speed ADCs, and uses time interleaving method and AFB filter bank to achieve the performance that can not be achieved by a single civil ADC (as of the date of this paper). Fig. 6 shows broadband dynamic performance data and compares analog and digital adjustment methods. With “manual adjustment”, the gain and phase of each channel at 128 MHz can reach the matching degree of 14 bit (86 DBC), but the performance decreases very fast: the bandwidth of 12 bit (74 DBC) performance is only 20 MHz. On the other hand, the digital adjustment method can maintain better than 12 bit performance in the whole test range of 170 MHz — the obvious performance advantage brought by the well-designed digital post-processing method.
Therefore, when the system design requires the sampling rate to be higher than the sampling rate of a single ADC available in the market, it is valuable to consider the time interleaving method. If it is necessary to maintain 10 ~ 12 bit performance in the whole Nyquist frequency band, integrated solutions, such as ad12400 and ad12500, give play to the advantages of time interleaving method because they successfully overcome the difficulties related to strict channel matching requirements.
Signal average and time interleaving
Here we have summarized two methods that can surpass the performance of a single ADC currently available. We have given examples of multi chip products that can provide high performance using these two methods. In fact, such standard products have been put on the market – solving design problems and providing standard technical specifications – enough to meet the needs of many customers. However, the following explanation is beneficial to users who want to further study the application field of using standard single ADC or multi-channel non configured ADC to improve performance.
SNR is a common measure to compare topology. Assuming that the selected ADC is ad9444 and the system design requires 40 MHz bandwidth and 79 DB typical SNR, we can consider signal average and time interleaving. Both methods need to use four ad9444 in order to improve the inherent SNR of ad944 by 5 ~ 6 dB. Because the two methods play equal roles in noise reduction, further trade-offs are needed to reflect the market space of typical design.
Firstly, the signal averaging method is not as complex as the time interleaving method. The clock required by the four ADCs in the signal averaging circuit can be obtained from a resistive distributor, a magnetic distributor or a simple 1:4 fan out clock distribution IC. The time interleaving method needs to use at least two D flip flops to realize the 4-frequency division and 90 ° interval phase sequence functions. In some cases, four additional flip flops may be required to buffer the timing signal to maintain strict timing. In order to achieve the desired 6 dB SNR improvement, the time interleaving method may require the use of digital filters, which require real-time multipliers and adders (if used in system design, or some processing time). However, the signal averaging method only needs a real-time adder, which really reduces the number of digital logic circuits.
The effectiveness of each noise reduction method must also be carefully considered. In particular, it is necessary to understand the relevant noise and bandwidth level of each channel. Because with the increase of correlation noise between channels, the effectiveness of signal averaging method will be lower and lower. In the system where jitter and phase noise are the main noise sources, the risk of related noise will affect the improvement of SNR.
The time interleaving method actually spreads the noise in the range of 4 times the bandwidth, and then filters out the useless 120 MHz. In this case, we must study and master the broadband characteristics of noise spectrum. If the noise spectrum content of the channel is evenly distributed in the whole 160 MHz Nyquist band, this method can improve 6 dB SNR. However, if the noise distribution is mainly concentrated within the useful 40 MHz bandwidth, the goal of improving 6 dB SNR may not be achieved.
Another important consideration in comparing the two methods is frequency planning. If a single frequency system is used and its input frequency is more than 1 / 4 of the single ADC sampling rate (e.g. 20 MHz), the 2nd, 3rd, 4th, 5th and 6th harmonics fall outside the 40 MHz useful frequency band. Therefore, these higher harmonics will be reduced or filtered by digital noise filter. In addition, the image spurious signal discussed above will also fall outside the useful frequency band and be filtered out. In multi frequency system, some harmonic components will also fall outside the useful bandwidth, which will reduce the total harmonic distortion of the system.
In conclusion, the signal averaging method provides a simple method to improve 6 dB SNR, and the time interleaving method provides some benefits worth considering for the development of system architecture.
Use of multichannel ADC system
Multichannel ADC has played an important role in improving digital acquisition system. The imaging system optimizes the signal by summing the multi-channel ADC to improve the definition. Digital oscilloscope manufacturers have developed ADC time interleaving method to meet the requirements of high sampling rate. Other receiving systems using frequency division multiple access (FDMA) also use multiple ADC channels to divide the frequency band — reducing the demand for each ADC input bandwidth, so as to further increase the dynamic range. In order to save power consumption and size, there are more and more ADCs packaged with 4-channel ADC and 8-channel ADC multichannel IC. They are being used to develop multichannel system architecture to provide unprecedented function and performance.
Responsible editor: GT