Train operation monitoring and recording device has played a huge role in the process of railway transportation safety. Its disadvantage is that it has no audio and voice recording function. In order to solve this problem, according to the technical requirements of the Ministry of railways, a new type of train audio and voice recording equipment is developed. The equipment is mainly used for collaborative monitoring device to analyze traffic accidents, use relevant technology to record the status information of equipment operation, and record the joint control of crew locomotives, which provides a new technical means for the scientific management of the maintenance department and transportation department. In view of the technical indexes and standards of common equipment, for audio digitization, the sampling frequency is 44.1KHz and the quantization accuracy is 16bit. In terms of coding, MPEGI layer II compression coding is adopted; for voice digitization, the sampling frequency is 16KHz and the quantization accuracy is 16bit. In terms of coding, MPEG-2 compression coding is adopted.
1. Hardware system composition
The overall structure of the monitoring and recording equipment is shown in Figure 1. The whole system is composed of a / D conversion chip, digital signal processor DSP, CPLD controller, flash mass memory and LCD display.
In this system, the A / D conversion chip is used to complete the signal conversion, and the data format can be selected between 16, 18 and 20 bits; the digital signal processor (DSP) is the core digital processor of the system, which has powerful function to complete the compression and coding of digital signal; CPLD is used for the control of data transmission and the initialization detection setting of a / D converter, flash memory and LCD display; fla is used for the control of data transmission SH large capacity memory is used for data storage; LCD screen is used to display the status of the current system, such as running waiting, data processing, etc. After the system is powered on, if there is an audio / voice signal input into the A / D converter, the type of the input signal is judged by interruption and inquiry, and then the analog / digital format conversion of the audio / voice signal is carried out. A series of digital signals obtained are sent to the DSP for data compression coding, and then stored in the flash mass memory by CPLD. The whole system works in pipeline mode, data acquisition, compression coding and storage are carried out at the same time.
1.1 audio / voice processor UDA1341TS
UDA1341TS is a single-chip stereo A / D and D / a converter produced by Philips company. It has low power consumption, 3.0V working voltage, 97dB signal-to-noise ratio, dual channel input function, and the sampling frequency is between 16KHz, 32kHz and 44.1KHz.
Udal341ts and DSP constitute the audio / voice signal acquisition system, which mainly involves the sampling clock in place (BCK), word synchronization clock (WS), sampling data output (Data0), system clock input (sysclk) which have time sequence requirements. In the system, Data0 is used as the output pin and connected with bdr0 pin of DSP; BCK, WS and sysclk are used as the input pins, and their timing is supplied by DSP. The system clock of UDA1341TS can only be 256fs, 384fs and 512fs. By programming sc0 bit and SC1 bit of the status register, the system clock can be selected and set. Here FS is the sampling frequency of audio / speech signal. During data sampling, WS is used to indicate the valid data output from Datao of UDA1341TS. When the system samples the vinl (left channel) port, the rising edge of WS indicates the beginning of a frame of data, and the falling edge indicates the end of a frame of data; when the system samples the vinr (right channel) port, the falling edge of WS indicates the beginning of a frame of data, and the rising edge indicates the end of a frame of data.
UDA1341TS provides a L3 port. The three pins of L3, l3data, l3mode and l3clock, are programmed by CPLD controller to set its internal registers. When l3mode pin is at low level, register address information is input through l3data pin; when l3data pin is at high level, data information about register setting is input through l3data pin (such as setting chip system clock frequency, data input format, chip working mode, etc.). UDA1341TS is connected with McBSP (multi-channel buffered synchronous serial port) of DSP. All kinds of synchronous signals are generated by DSP, which ensures the normal reception of new data and the normal processing of received data. The hardware connection diagram between UDA1341TS and DSP is shown in Figure 2.
1.2 audio / speech coder TMS320VC5402
The compression of digital audio / voice signal needs a lot of digital signal processing, which can not be completed by single chip microcomputer. Therefore, the DSP chip TMS320VC5402 (hereinafter referred to as “c5402”) of TI company is selected to compress the audio / voice signal. “C5402 is a 54x series fixed-point DSP produced by TI company in October 1999. Its operating speed reaches 100 MIPs. It has an enhanced multi bus structure, three independent 16 bit data memory buses and one program memory bus. It has a 40 bit arithmetic logic unit, including two independent 40 bit adders, a 17 bit × 17 bit parallel multiplier and a 40 bit barrel shifter. It supports single instruction cycle Memory block move instruction provides efficient program and data memory management, supports parallel storage and parallel loading arithmetic instruction, conditional storage instruction and interrupt fast return, and supports fixed-point DSPC language compiler.
C5402 communicates with UDA1341TS through its McBSP. McBSP provides full duplex communication mechanism, double buffered transmit register and three buffered receive register, allowing continuous data stream transmission, and the data width is between 8, 12, 16, 20, 24 and 32 bits; the communication between McBSP and audio / speech processor is realized by bdro pin, and the control of communication process is realized by bclkro, bclkr1 and bfsro pins.
1.3cpld low speed control
DSP as a high-speed processor is not suitable for low-speed control applications. In this system, the detection and initialization of UDA1341TS, the control of LCD and the storage control of flash are all low-speed control. This system uses epm7128scpld of Altera company to complete these tasks, which brings great convenience to the programming and debugging of the system and shortens the development cycle.
2. Operation software development
The software design mainly includes the compression and coding of audio / speech data and error checking of audio / speech data.
2.1 audio / voice data coding
In the aspect of audio coding algorithm, the current general MPEGI layer erii compression coding algorithm is adopted. The algorithm is frame data structure coding, and the sample value of a frame is 1152. Based on the 44.1KHz sampling frequency of processor UDA1341TS, the coding of a frame data is required to be completed within 26ms. MPEG-2 compression coding algorithm is used in speech coding. MPEG-2 algorithm is an extension of mpeg-i algorithm. The sample value of a frame is 576, which is calculated by the 16KHz sampling frequency of processor UDA1341TS. The encoding of a frame is required to be completed within 72ms. The instruction cycle of “c5402” is 10ns. For the MPEG algorithm here, when it meets the requirements of the algorithm, it takes up to 15ms for dual channel real-time coding, so “c5402” can complete the real-time coding of the algorithm. The algorithm flow is shown in Figure 3, which mainly includes the following aspects: (1) the operation of filter bank. (2) The operation of psychoacoustic model. (3) Quantization coding. (4) Frame data format.
The function of filter banks is to complete the signal mapping from time domain to frequency domain. The calculation of psychoacoustic model is to use 1024 points FFT to analyze the spectrum of the input audio / speech signal, and then calculate the masking characteristics of each subband based on the results of time-frequency mapping. Quantization coding is a process of calculating the bit allocation information required for each subband coding according to the masking characteristics of each subband ear and the requirements of output bit rate, and linear quantization coding for each subband data. The follow-up work of the program is to format the data according to MPEG standard, so that the data can be decoded correctly after encoding. The main program flow chart of the system is shown in Figure 4.
Intra coding is that DSP compresses the digital audio / speech signal from a / D converter according to MPEG standard. The process is shown in Figure 5.
2.2 data error checking
2.2.1 calibration principle
CRC-16 is used to check the error of audio and voice data, that is, the processed data block can be regarded as an n-order binary polynomial D (x), for example, a 16 bit binary number 10100101 can be expressed as: x15 + x13 + X10 + X8 + X7 + X5 + x2 + 1. The multiplication and division of polynomials is the same as the multiplication and division of ordinary algebraic polynomials. The addition and subtraction of polynomials takes 2 as the module for logical XOR operation. When CRC is used, the sender and receiver use the same generating polynomial s (x), and the coefficients of the first and last bits of S (x) must be 1. In this algorithm, s (x) uses polynomial. The processing method of CRC is: the sender removes the data d (x) to be processed by generating polynomial s (x), and obtains the remainder as CRC check code. When checking, the error of data frame is judged by whether the calculated correction result is 0 or not.
2.2.2 implementation of verification algorithm
The key of CRC check with c5402 is to use its 40 bit accumulator a as shift register to realize modular 2 polynomial division of CRC code. At this time, CRC-16 code occupies the upper 16 bits of accumulator a, and the rest of the bits complement 0. In the operation, SFTA (arithmetic shift) and XOR (XOR) instructions are used to complete the code shift and XOR operation in the coding process, and XC instructions are used to complete the judgment execution of conditional statements. “C5402 provides a special instruction bitt. Bitt takes out the (15-t) bit of a 16 bit data by register T and sends it to TC (TC is a bit in the special register). The specific algorithm steps are shown in Figure 6.
(1) First, the high 16 bits of CRC shift register a (i.e. remainder register) are initialized to all o, and the remainder is cleared to 0.
(2) Move the value in CRC shift register a to the left by one bit, that is, the maximum shift into C, and then use the instruction bitt to take out the highest bit of input check data and send it to register B to judge whether the highest bit moved in C is 1 after XOR with the highest bit of input check data.
(3) If it is 1, XOR the value in register a with the generating polynomial x16 + x15 + x2 + 1 in input register B, and then skip to step (2) to process the next bit; if it is not 1, skip to step (2) to process the next bit directly. Repeat the above-mentioned left shift and XOR judgment until all the input data bits are processed, then the highest 16 bits of register a is the remainder after polynomial division, at this time, the highest 16 bits of register a is CRC check code.
After power on and running, the system runs stably through many experiments. At present, the equipment has been used for on-site debugging, and some of it has been loaded and operated, which meets the actual requirements of train monitoring and recording.
Editor in charge: GT