By Rob Reeder
The importance of analog bandwidth is higher than everything else, which is reflected in more and more applications. With the emergence of GSPS or rfadc, the Nyquist domain has increased tenfold in just a few years to reach the multi GHz range. This has helped broaden the horizons of the above applications, but more bandwidth is still needed to reach the X-band (12GHz frequency). The use of sample and hold amplifier (THA) in the signal chain can fundamentally expand the bandwidth, far beyond the ADC sampling bandwidth, and meet the needs of demanding high bandwidth applications. This paper will prove that adding a THA in front of the latest converter developed for the RF market can achieve more than 10GHz bandwidth.
GSPS converter is popular at present. Its advantage is that it can not only shorten the RF signal chain, but also create more resource structures in FPGA for use, such as reducing the down conversion of the front end and the digital down converter (DDC) of the later stage. However, a considerable number of applications still require high-frequency raw analog bandwidth (BW), which is far beyond the level that RF converters can achieve. In such applications, especially in the national defense and instrumentation industry (wireless infrastructure is the same), there is still a need to fully expand the bandwidth to 10GHz or above. The coverage exceeds C-band, and more and more applications need to cover X-band. With the progress of high-speed ADC technology, the demand for high-speed and accurate resolution of ultra-high intermediate frequency (if) in GHz region is also increasing. The baseband Nyquist domain has exceeded 1GHz and is rising rapidly. This statement may be out of date by the time this article is published, because it has developed very rapidly.
This brings two challenges: one is the converter design itself, and the other is to couple the signal to the front-end design of the converter, such as amplifier, balun and PCB design. The better the performance of the converter, the higher the requirements for the front-end signal quality. More and more applications require high-speed GSPS converters with a resolution of 8 to 14 bits. However, the signal quality of the front end has become a bottleneck – the short board of the system determines the index of the whole project.
Broadband defined in this paper refers to the use of signal bandwidth greater than hundreds of MHz, and its frequency range is from near DC to 5ghz-10ghz. This paper will discuss the use of broadband THA or active sampling network, in order to realize the bandwidth up to infinity (sorry, there is no toy story emoticon available at present), and focus on its background theory, which supports the expansion of rfadc bandwidth, which may not be available by itself. Finally, this paper will illustrate some considerations and optimization techniques to help designers achieve practical broadband solutions for UWB applications.
Lay a good foundation
For radar, instrumentation and communication applications, high GSPS converter is widely used because it can provide a wider spectrum to expand the system frequency range. However, the wider spectrum poses more challenges to the internal sample holder of the ADC itself, because it is usually not optimized for UWB operation, and the ADC generally has limited bandwidth, and its high-frequency linearity / SFDR will decrease in these higher Analog bandwidth regions.
Therefore, using a separate THA in front of the ADC to expand the analog bandwidth has become an ideal solution, so that the analog / RF input signal with very high frequency can be sampled at a precise time. This process realizes signal sampling through a low jitter sampler, and reduces the dynamic linearity requirements of ADC in a wider bandwidth, because the sampling rate remains unchanged during RF analog-to-digital conversion.
The benefits of this scheme are obvious: the analog input bandwidth is fundamentally expanded, the high-frequency linearity is significantly improved, and the high-frequency SNR of tha-adc module is improved compared with the performance of rfadc alone.
Tha characteristics and overview
ADA’s tha series products can provide precision signal sampling in the bandwidth range of 18GHz, and have 9-10 bit linearity, 1.05mv noise and random aperture jitter performance of 70fs in the input frequency range of DC to more than 10GHz. The device can work with 4gsps with minimal loss of dynamic range. Specific models include hmc661 and hmc1061. These track and hold amplifiers can be used to expand the bandwidth and / or high-frequency linearity of high-speed analog-to-digital conversion and signal acquisition systems.
Taking the single-stage thahmc661 as an example, the output is composed of two segments. In the sampling mode interval of the output waveform (positive differential clock voltage), the device becomes a unit gain amplifier. Under the constraints of input bandwidth and output amplifier bandwidth, it copies the input signal to the output stage. During the positive clock to negative clock transition, the device samples the input signal with a very narrow sampling time aperture, and maintains the output at a relatively constant value representing the sampling time signal within the negative clock interval. In front-end sampling with ADC, single-stage devices are often preferred (ADI has a two-stage tha model hmc1061). The reason is that most High-Speed ADCs have integrated a tha internally, and its bandwidth is usually much smaller. Therefore, adding a tha before the ADC constitutes a composite two-stage component (or a three-stage component, if two-stage hmc1061 is used), and the THA is in front of the converter. When using the same technology and design, the linearity and noise performance of single-stage devices are usually better than those of two-stage devices because there are fewer stages of single-stage devices. Therefore, single-stage device is often the best choice for front-end sampling with high-speed ADC.
Delay mapping THA and ADC
One of the most difficult tasks in developing the sample holder and ADC signal chain is to set an appropriate timing delay between the time tha captures the sampling event and the time it should be moved to the ADC to resample the event. The process of setting the ideal time difference between two efficient sampling systems is called delay mapping.
Figure 1. Sample and hold topology: (1a) single column, (1b) double column.
Fig. 2. Delay mapping circuit.
Completing this process on the circuit board may be tedious, because the paper analysis may not consider the corresponding delay caused by the clock routing propagation interval on the PCB, the internal device group delay, the ADC aperture delay, and the related circuits involved in dividing the clock into two different segments (one clock routing is for THA and the other clock routing is for ADC). One way to set the delay between THA and ADC is to use a variable delay line. These devices can be active or passive in order to correctly align the time of tha sampling process and give it to ADC for sampling. This ensures that ADC samples the stable holding mode part of tha output waveform, so as to accurately represent the input signal.
As shown in Figure 2, hmc856 can be used to start the delay. It is a high-speed QPS, or a 32-bit QPS, inherent delay of 905. Its disadvantage is to set / traverse each delay setting. To enable the new delay setting, each bit / pin on the hmc856 needs to be pulled to negative voltage. Therefore, it will be a cumbersome task to find the best delay setting in 32 combinations by welding pull-down resistors. In order to solve this problem, ADI uses serial controlled SPST switch and off board microprocessor to help complete the delay setting process faster.
In order to obtain the best delay setting, a signal is applied to the combination of THA and ADC, which should be outside the ADC bandwidth range. In this example, we select a signal of about 10GHz and apply the level of – 6dbfs (captured on the FFT display). The delay setting is now scanned in binary steps, and the level and frequency of the signal remain constant. Display and capture FFT during scanning, and collect the fundamental power and spurious free dynamic range (SFDR) values corresponding to each delay setting.
As a result, as shown in Fig. 3a, the fundamental power, SFDR and SNR will vary with each setting applied. As shown in the figure, when the sampling position is placed in a better place (in the process of tha sending samples to ADC), the fundamental wave power will be at the highest level, and the SFDR should be at the best performance (i.e. the lowest). Fig. 3b is an enlarged view of the delay mapping scan. The delay set point is 671, that is, the delay should remain fixed in this window / position. Remember that the delay mapper is only valid for the relevant sampling frequency of the system. If the design requires a different sampling clock, it needs to be rescanned. In this example, the sampling frequency is 4GHz, which is the highest sampling frequency of tha device used in the signal chain.
Fig. 3a. Mapping results of signal amplitude and SFDR performance on each delay setting.
Fig. 3B. Mapping results (amplification) of signal amplitude and SFDR performance on each delay setting.
Front end design for a large amount of raw analog bandwidth
First, if the key goal of the application is to handle 10GHz bandwidth, we should obviously consider RF mode. Note that the ADC is still a voltage type device and will not consider power. In this case, the word “match” should be used with caution. We find that it is almost impossible to match a converter front end with a 100MSPS converter at each frequency; Rfadc with high frequency bandwidth will not be much different, but the challenge remains. The term “match” shall mean an optimization that produces the best results in the front-end design. This is an all inclusive term, in which input impedance, AC performance (SNR / SFDR), signal driving strength or input driving, bandwidth and passband flatness can produce the best results for this particular application.
Finally, these parameters jointly define the matching performance of the system application. When starting the broadband front-end design, the layout may be the key, and the number of devices should be minimized to reduce the loss between two adjacent ICs. Both are important for optimal performance. Be careful when connecting analog input networks together. Routing length and matching are the most important, and the number of vias should be minimized, as shown in Figure 4.
Figure 4. THA and ADC layout.
Figure 5. THA and ADC front-end network and signal chain.
The signal is connected to the tha input through differential mode (we also provide a reference design link for single ended RF signal input) to form a single front-end network. In order to minimize the number and total length of vias, we are particularly careful here to keep vias from passing through these two analog input paths and help offset any pins in the routing connection.
The final design is quite simple, and only a few points need to be paid attention to, as shown in Figure 5. 0.01 used μ The f capacitor is a broadband type that helps keep the impedance flat over a wide frequency range. Typical finished product 0.1 μ F capacitor can not provide flat impedance response, which usually causes more ripple in passband flatness response. The 5 Ω and 10 Ω series resistors at tha output and ADC input help to reduce the peaking of tha output and minimize the distortion caused by residual charge injection of ADC’s own internal sampling capacitor network. However, these values need to be carefully selected, otherwise it will increase signal attenuation and force tha to improve driving strength, or the design may not be able to utilize the full range of ADC.
Finally, differential shunt termination is discussed. This is critical when connecting two or more converters together. In general, a light load (e.g., a 1K Ω load at the input) helps to maintain linearity and contain the reverberation frequency. The 120 Ω shunt load of the diverter also has this effect, but it will produce more actual load, 50 Ω in this example, which is the load tha wants to see and optimize.
Now look at the results! Checking the signal-to-noise ratio or SNR in Figure 6, it can be seen that 8-bit ENOB (significant digits) can be realized in the range of 15GHz. This is quite good. Think that you may have paid $120000 for a 13GHz oscilloscope with the same performance. As the frequency moves toward the L, s, C, and X bands, the integrated bandwidth (i.e., noise) and jitter limits begin to become significant, so we see a roll down in performance.
It should also be noted that in order to keep the level between THA and ADC constant, the full-scale input of ADC is internally changed to 1.0vp-p through SPI register. This helps to keep THA in the linear region because its maximum output is 1.0vp-p differential.
Figure 6. Snrfs / SFDR performance results at – 6dbfs.
Linearity results or sfrd are also displayed. Here, the linearity up to 8GHz exceeds 50dbc, and the linearity up to 10GHz exceeds 40dbc. In order to achieve the best linearity over such a wide frequency range, the design here is optimized using the analog input buffer current setting characteristics of ad9689 (through SPI control register).
Figure 7 shows the passband flatness, which proves that adding a tha before rfadc can achieve 10GHz bandwidth, so as to fully expand the analog bandwidth of ad9689.
Figure 7. THA and ADC networks and signal chains – bandwidth results.
For applications that require optimal performance over multi GHz analog bandwidth, tha is almost essential, at least for now! Rfadc is catching up quickly. It is easy to understand that when sampling a wide bandwidth to cover multiple target bands, the GSPS converter has the advantage of ease of use in theory, which can eliminate one or more down mixing stages on the front-end RF band. However, achieving a higher range of bandwidth may pose design challenges and maintenance problems.
When using THA in the system, ensure that the location of sampling points is optimized between THA and ADC. Using the delay mapper described in this article will produce the best overall performance results. Understanding the program is tedious, but it is very important. Finally, it should be remembered that matching the front end actually means achieving the best performance under a given set of performance requirements of the application. When sampling at X-band frequency, Lego method (simply connecting 50 Ω impedance modules together) may not be the best method.
Apply notes. Use hmc661lc4b to improve the bandwidth and performance of high-speed analog-to-digital converter. ADI, 2011.
Apply notes. Understand high speed ADC testing and evaluation. ADI, 2015.
Jim Caserta and rob Reeder“ Design considerations for the front end of broadband analog-to-digital converter II: using amplifier or transformer to drive ADC? “. Mock dialogue, Vol. 41, February 2007.
Hmc10611lc5 data book. Adi.
Hmc661lc4b data book. Adi.
Ramya ramachadran and rob Reeder“ Design considerations for the front end of broadband analog-to-digital converter: when to use dual transformer configuration “. Mock dialogue, Vol. 40, July 2006.
RobReeder。“ Transformer coupling front end of broadband analog-to-digital converter “. Mock dialogue, Vol. 39, April 2005.
The author would like to thank Mike Hoskins, the designer of hmc661 and hmc1061tha, for providing background knowledge, and chasfrick and John Jefferson for compiling and running most of the data in the laboratory.
RobReeder［rob. [email protected] ] is a senior system application engineer of ADI high speed converter and RF application group (located in Greensboro, North Carolina). He has published a large number of articles on converter interfaces, converter testing and analog signal chain design for various applications. Rob has been an application engineer in the Department of aerospace and defense for five years, focusing on various application fields such as radar, EW and instrumentation. Previously, he also worked in the high-speed converter product line for 9 years. Before that, rob also engaged in test development and Simulation Design (working for ADI multichip products group), with 5 years of experience in space, defense and highly reliable application analog signal chain module design. Rob received a bachelor’s degree in Electronic Engineering (BSEE) and a master’s degree in Electronic Engineering (MSEE) from the University of Northern Illinois (dicarbur, Illinois) in 1996 and 1998, respectively. When rob doesn’t write articles or study circuits in the laboratory in the evening, he likes to exercise in the gym, listen to electronic music, make furniture from old boards, and most importantly, relax with his two children.