Key words: FPGA, domestic, domestic FPGA, trial

Author: privileged students

There are some questions about the configuration of code and data storage area. Please answer them:

Q: code memory can be OTP or extension memory. Generally, there is no problem using OTP after the final software is finalized, but extension memory will be selected during debugging. There are three types of extension memory: EMB, SRAM and custom. Generally, the code memory should be nonvolatile memory, while the EMB and SRAM listed here are power down volatile. I don’t quite understand this? Can we say that extension memory is only the storage area where the code runs when keilc is in debug mode, rather than the medium for code power down storage? The EMB is only 1K (up to 2K). If this code memory is set, can the code not exceed 1K when keilc debug is set?

FAE: both EMB and SRAM are volatile. EMB can support up to 2KB of code space. The initialization information of EMB and FPGA configuration information are stored in the embedded SPI flash and loaded automatically when powered on. When using SRAM, we need to use the sramloader project provided by us and use the reconfiguration characteristics of Astro.

Q: for questions similar to the above, there are two options for data storage. On ship SRAM is checked by default. There is no doubt about this. FP should be 4m flash with internal expansion, and it should be nonvolatile memory. Data memory usually doesn’t need to be nonvolatile, right? I think as a rule, code storage is nonvolatile memory and data storage is volatile memory, and your configuration options confuse me a little.

FAE: Astro internally provides 16kb special SRAM for 8051, which is used as data space.

Q: in addition, SPI burning should burn FPGA configuration data into 4m flash? The function of configuration packer should be to package the FPGA configuration data and software hex file into a file and burn it into 4m flash? I’ve tried this. It seems that the system doesn’t run after the power is off. Is there something particular about the memory configuration of the system?

FAE: configuration packer allows Astro to store multiple configuration files in memory. It can be used to package sramloader project for power on automatic loading when SRAM is used as code space. In the attachment are several application documents about Astro. Please have a look first. They are written in detail. I believe they will be very helpful for you to understand the usage of Astro. Thank you!

Yesterday, we bombarded the FAE responsible for hardware of agate logic, and had a deeper understanding and understanding of its development tools and device structure. The above questions and answers were only about the data and code memory of 51 hard core. After a lot of questioning, we finally forced out several decent documents, and did some practice after digestion, Then I have a little harvest and some feasible ideas on the memory configuration of subsequent projects. In addition, some questions about timing have also been answered. I’m not very relieved. I’ve also asked some real “questions”, and I’ve asked some bugs in the software version currently in use. At present, I still need to wait for the manufacturer to provide me with patches, so the blog on timing can only be postponed.

The questions raised by privileged students are quite up to standard, but they are not very standard. FAE’s answer is not easy to understand. Finally, the document gives a more authoritative answer.

Before discussing the software operation mode of Astro series chip 51 hard core, we should first see what on-chip storage resources Astro series chips have provided. It doesn’t matter. It’s a surprise to see – it can be said that there are a wide range of products to meet all kinds of needs.

1. A total of 1mbit OTP storage area, of which 64KB is used for FPGA configuration data storage and 64KB is used for 51 hard core final code memory.
2. 4Mbit (512KB) FPGA and 8051 public SPI flash.
3. Two 9kbit configurable dual port EMBs.
4. 16kb 51 hard core dedicated data memory.

Main operation modes of Astro series chip 51 hard core software:

Mini mode:

No external memory, using the existing resources of the chip, FPGA configuration data and 8051 code (less than 2KB) are stored in SPI flash. The data in the flash system is initialized from the FPGA and then exported from the SPI configuration software; After completion, the 8051 code runs directly from the EMB.

When the embedded 8051 has no waiting cycle, the fastest clock frequency can reach 70MHz and the performance can reach 47mips. It is mainly used for debugging and production when there are few 8051 codes, and the cost is relatively low.

The test in Note 2 is based on this mode, and the performance is OK.

Debugging mode:

External SRAM memory, FP bootloader configuration data, FPGA user program configuration data and 8051 user code are stored in SPI flash in sections. When the system is powered on, first export the FP bootloder configuration data (including the loader part) from SPI flash. Configuring FP includes the initialization data of EMB. After completion, SRAM loader program will carry 8051 user code into external SRAM; Then import FP user program from SPI flash and reconfigure FP, and 8051 code starts running in external SRAM.

When the embedded 8051 has no waiting cycle, the fastest clock frequency can reach 35MHz and the performance can reach 23mips. This mode is mainly used for debugging when 8051 code exceeds 2KB. Of course, it can also be used in production. Please note that plug-in SRAM will increase the cost.

Since this mode is unlikely to be used, privileged students do not study it much, but it is also a common bootloder mode in embedded systems.

Final production mode:

There is no external memory, 8051 code is stored in OTP memory, and FP configuration data is stored in OTP or SPI flash. Because OTP memory is disposable, it cannot be used in the debugging phase. Generally, OTP memory can be used after the final finalization of products to obtain the best performance and the lowest cost.

When OTP is used as 8051 code memory, the maximum clock frequency can reach 100MHz. The ideal method is to use PLL to generate 8051 clock. The lower 4 bits of ckcon SFR are used to control the waiting period of data memory. If the clock frequency of 8051 is higher than 45mhz, it is better to set value to be greater than or equal to 2 to prevent the clock from being too fast and the data is not ready.

In other words, OTP can achieve the best performance of 51 hard core code, and even the speed bottleneck of performance is not code access, but data access.

The above three modes are recommended, but the privileged students consider from the actual engineering needs. In short, they need a debugging mode and a production mode. It is indisputable to choose OTP burning for the production mode, while the debugging mode is a little tricky. If you choose the small mode, the amount of code running is too small, at most 2K, and you can’t do anything. If you choose to expand SRAM, limited IO resources will not be allowed. So, it’s a little distressed, but fortunately, there’s a second choice – the fourth mode with low performance.

When the performance of 8051 is lower than 1.4mips, SPI flash can be used as the code memory of 8051. The operating environment of this mode is as follows:

1. Select on-chip SPI flash;

2. FPGA configuration data and 8051 code are stored in the same SPI flash;

3. About 90 LE cells are required for the interface between 8051 and SPI flash;

4. The fastest core clock of 8051 is about 30MHz, and the fastest running performance of 8051 is about 1.4mips;

5. Sequential fetch requires 8 clock cycles, and jump fetch Requires 40 cycles;

When trying SPI flash mode, I encountered something interesting. Privileged students do the running test of SPI flash according to the example, and the results are uncertain, and they can’t find the relevant IP core. So I asked FAE. FAE directly told me that the IP core had not been integrated into the tool, and then sent all the source code. Hehe, although the tools are not perfect, the service is very considerate.

Because the mode based on SPI flash is to use FPGA logic to build a flash reading module between 51 hard core and SPI flash. Therefore, after testing, it is true that the frequency of the logic module of flash reading control can not be too high. If it is too high, flash will * *. The theoretical value is 30m, while the privileged students use 25m. Then use the same method in the previous note to change the frequency of the hard core for testing.

Delay Functions

 

EMB mode

 

SPI flash mode

 

50MHz

 

100MHz

 

50MHz

 

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