1. Design of axi2mem conversion interface

The axi2mem conversion interface needs to convert the Axi signal (with a clock of 250MHz or 500MHz) from PCIe into a MEM interface with a 100MHz clock. The MEM interface is used for the main port of SoC Bus and for reading and writing internal modules or configuration registers of the chip.

Three key points of Axi interface design

2. Key point 1: those who can do more work, complex processing in the fast clock domain and simple processing in the full clock domain.

The cycle of the fast clock domain is short. In order to improve the rate, try to complete the complex processing in the fast clock domain. For example, if the Axi to MEM interface needs 8 cycles to write data, these 8 cycles can be allocated to a 250 / 500MHz clock or a 100MHz clock. In order to improve the transmission rate, we should allocate more processing cycles to the 250 / 500MHz clock. The rate of five 250 / 500MHz cycle operations + three 100mh cycles is certainly greater than that of three 250 / 500MHz cycle operations + five 100MHz cycles.

3. Point 2: how fast the receiver responds, how fast the sender can send, and try to optimize the response cycle

Axi3 and axi4 buses have write response channels. Write response can only be carried out after writing data. The write response cycle of the Axi converter limits the sending rate of the data sender. If the write response cycle of the Axi adapter is long, the response cycle received by the PCIe at the receiving end is long, and the number of outstanding requests received by the PCIe at the receiving end is limited. Therefore, when the number of outstanding requests at the receiving end reaches the upper limit, the Axi adapter processes a write response, and the PCIe at the transmitting end can continue to send a write request, so try to optimize the response rate, Reduce response cycles.

4. Key point 3: the module reset signal adopts chip power on reset power_ on_ reset,

The Axi to MEM module and SoC Bus require the reset driven by the chip power on reset signal. Because the SoC Bus is configured, it is required that the chip can be used when the chip is powered on.

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