IIC bus overview

IIC was developed in 1982 to provide easier interconnection between CPU and peripheral chips in TV. Television is one of the earliest embedded systems, and the original embedded system used memory mapped I / O to interconnect microcontrollers and peripherals. To realize memory mapping, the device must be connected to the data line and address line of the microcontroller in parallel. This method requires a large number of lines and additional address decoding chips when connecting multiple peripherals, which is very inconvenient and costly.

In order to save the pins of microcontroller and additional logic chips, make the printed circuit board simpler and lower cost, Philips laboratory in the Netherlands has developed IIC (inter integrated circuit), which is a serial bus composed of data line SDA and clock line SCL, which can send and receive data. Bidirectional transmission between CPU and controlled IC and between IC and IC

IIC data transmission rates include standard mode (100kbps), fast mode (400kbps) and high-speed mode (3.4mbps). Other variants implement low-speed mode (10kbps) and fast + mode (1Mbps)

IIC bus hardware structure

IIC, i.e. I2C, is a bus structure.

The circuit structure of SDA and SCL pins inside each I2C bus device is the same, and the output drive of the pin is connected with the input buffer. The output is an open drain FET and the input buffer is an in-phase device with high input impedance. This circuit has two characteristics:

Because SDA and SCL are open drain structures, the “line and” logic of the signal is realized with the help of external pull-up resistance;

While the pin outputs the signal, it can also detect the level on the pin to detect whether it is consistent with the output just now. Provide hardware foundation for “clock synchronization” and “bus arbitration”.

This paper interprets the FPGA implementation principle and process of IIC bus

Typical application of IIC bus

Typical application of IIC equipment:

This paper interprets the FPGA implementation principle and process of IIC bus

Physically, the IIC system consists of a serial data line SDA and a serial clock line SCL. The host addresses and transmits information to the slave according to a certain communication protocol. During data transmission, the host initiates a data transmission. While the host transmits the data on the SDA line, it also transmits the clock through the SCL line. The object and direction of information transmission and the start and end of information transmission are determined by the host.

Each device has a unique address and can be a single receiving device (e.g. LCD driver) or a device that can receive or transmit (e.g. memory). The transmitter or receiver can operate in master mode or slave mode, depending on whether the chip must start data transmission or only be addressed.

FPGA implementation principle and process of IIC bus

1、 Experimental platform

Software platform: Modelsim Altera 6.4a (Quartus II 9.0)

Hardware platform: DIY_ DE2

2、 Experimental principle

1. Working principle of IIC bus device

The clock synchronization signal when transmitting information on IIC bus is completed by the logical “and” of all devices connected to SCL clock line. The jump from high level to low level on the SCL line will affect these devices. Once the clock signal of a device becomes low level, all devices on the SCL line will start and protect the low level period. At this time, the clock jump of devices with short low-level cycle from low to high does not affect the state of SCL line, and these devices will enter the state of high-level waiting.

When the clock signals of all devices change to high level, the low-level period ends, and the SCL line is released to return to high level, that is, all devices start their high-level period at the same time. Then, the first device that ends the high-level period pulls the SCL line to the low level. This generates a synchronization clock on the SCL line. It can be seen that the clock low-level time is determined by the device with the longest clock low-level period, while the clock high-level time is determined by the device with the shortest clock high-level period.

The data transmission rate on IIC bus can reach 100kbit / s in standard mode, 400kbit / s in fast mode and 3.4mbit/s in high-speed mode. The number of interfaces connected to the bus is only determined by the limit that the bus capacitance is 400pF.

2. Transmission protocol and data transmission timing of IIC bus

(1) Start and stop conditions

In the process of data transmission, the beginning and end of data transmission must be confirmed. In the IIC bus technical specification, the definition of start and end signals (also known as start and stop signals) is shown in Figure 1.

This paper interprets the FPGA implementation principle and process of IIC bus

Fig. 1 start and stop signal diagram

Start signal: when the clock bus SCL is at high level, the data line SDA jumps from high level to low level and starts transmitting data.

End signal: when SCL line is at high level, SDA line jumps from low level to high level to end data transmission.

The start and end signals are generated by the main device. After the start signal, the bus is considered to be in a busy state, and other devices can no longer generate the start signal. The master device exits the role of the master device after the end signal. After a period of time, the bus is considered idle.

(2) Data format

The IIC bus data transmission adopts the clock pulse bit by bit serial transmission mode. During the low level of SCL, the high and low levels on the SDA line can change. During the high level, the data on the SDA must be protected and stable so that the receiver can sample and receive. The timing is shown in figure 2.

This paper interprets the FPGA implementation principle and process of IIC bus

Fig. 2 data transmission sequence diagram

Each byte sent by IIC bus transmitter to SDA line must be 8 bits long, and the high bit is in the front and the low bit is in the back during transmission. Correspondingly, the main device generates 8 pulses on the SCL line; During the 9th pulse low level, the transmitter releases the SDA line, and the receiver pulls the SDA line low to give a reception confirmation bit; During the ninth pulse high level, the transmitter receives this acknowledgement bit and then starts the transmission of the next byte. During the first pulse low level of the next byte, the receiver releases SDA. Each byte requires 9 pulses, and the number of bytes transmitted each time is unlimited.

The data transmission format of IIC bus is that after the start signal of IIC bus, the first byte data sent is used to select the slave device address, in which the first 7 bits are the address code and the eighth bit is the direction bit (R / W). The direction bit “0” indicates transmission, that is, the master device writes the information to the selected slave device; A direction bit of “1” indicates that the master device will read information from the slave device. The format is as follows:

After the start signal, each device in the system compares its own address with the address sent by the main device to the bus. If it is consistent with the address sent by the main device to the bus, the device is the device addressed by the main device, and whether it receives or sends information is determined by bit 8 (R / W). Start sending data signal after sending the first byte.

(3) Respond

Data transmission must be responsive. The relevant response clock pulse is generated by the host. When the master device sends a byte of data, it then sends a clock (ACK) acknowledgement bit corresponding to the SCL line. At this time, the master device releases the SDA line in the clock, and the one byte transmission ends. The response signal of the slave device pulls the SDA line to a low level, so that the SDA is a stable low level during the high level of the clock. After the response signal from the device ends, the SDA line returns to the high level and enters the next transmission cycle.

Usually, the addressed receiver must generate a response after each byte received. When the slave cannot respond to the slave address, the slave must keep the data line high, and the master then generates a stop condition to terminate the transmission or a repeat start condition to start a new transmission. If the slave receiver responds to the slave address but cannot receive more data bytes after a period of transmission, the host must terminate the transmission again. This situation is represented by the fact that the slave does not generate a response after the first byte. The slave keeps the data line high and the master generates a stop or repeat start condition. The complete data transmission process is shown in Figure 3.

This paper interprets the FPGA implementation principle and process of IIC bus

Figure 3 complete data transmission process

In addition, IIC bus also has the function of broadcasting call address for addressing all devices on the bus. If a device does not need any data provided in broadcast call addressing, it can ignore the address and do not respond. If the device needs to broadcast the data provided on demand in call addressing, it shall respond to the address as a receiver.

3、 Experimental process

According to the above experimental principle, de2_ The IIC part of TV is simulated by Modelsim.

1. Simulation of clock required by IIC

FPGA is the host of IIC device. To generate the working clock of IIC, the clock signal required by IIC is simulated first.

The clock signal program to be simulated is as follows:

module I2C_Clock

iCLK,

iRST_N,

mI2C_CTRL_CLK,

mI2C_CLK_DIV,

mI2C_CLKO

);

input iCLK;

input iRST_N;

output mI2C_CTRL_CLK;

output mI2C_CLK_DIV;

output mI2C_CLKO;

reg mI2C_CTRL_CLK;

reg [15:0] mI2C_CLK_DIV;

reg mI2C_CLKO;

// Clock SetTIng

parameter CLK_Freq = 50000000; //??? 50 MHz

parameter I2C_Freq = 80000; //??? 40 KHz 25Us

parameter I2C_Thd = 200000; //??? 5Us 200 KHz

alw[email protected](posedge iCLK or negedge iRST_N)

begin

// 5000 TImes divide frequence of iCLK

if (!iRST_N)

begin

mI2C_CLK_DIV 《= 0;

mI2C_CLKO 《= 0;

mI2C_CTRL_CLK 《= 0;

end

else if( mI2C_CLK_DIV 《 (CLK_Freq/I2C_Freq))

begin

mI2C_CLK_DIV 《= mI2C_CLK_DIV+1;

if ((!mI2C_CTRL_CLK)&(mI2C_CLK_DIV 《 ((CLK_Freq/I2C_Freq)- (CLK_Freq/I2C_Thd))) )

mI2C_CLKO 《= 0;

else

mI2C_CLKO 《= 1;

end

else

begin

mI2C_CLK_DIV 《= 0;

mI2C_CTRL_CLK 《= ~mI2C_CTRL_CLK;

end

end

endmodule

The testbench procedure is as follows:

module I2C_Clock_tb ;

//parameter I2C_Thd = 200000 ;

//parameter I2C_Freq = 80000 ;

//parameter CLK_Freq = 50000000 ;

wire mI2C_CTRL_CLK ;

wire [15:0] mI2C_CLK_DIV ;

wire mI2C_CLKO ;

reg iRST_N ;

reg iCLK ;

I2C_Clock //#( I2C_Thd , I2C_Freq , CLK_Freq )

DUT (

.mI2C_CTRL_CLK (mI2C_CTRL_CLK ) ,

.mI2C_CLK_DIV (mI2C_CLK_DIV ) ,

.mI2C_CLKO (mI2C_CLKO ) ,

.iRST_N (iRST_N ) ,

.iCLK (iCLK ) );

iniTIal

begin

iRST_N = 0;

iCLK = 0;

#50

iRST_N = 1;

end

always

begin

#50 iCLK = ~iCLK;

end

endmodule

The waveform simulated by Modelsim is as follows:

This paper interprets the FPGA implementation principle and process of IIC bus

Figure 4 simulation diagram of IIC internal clock

After calculation, the clock frequency used in IIC is 40KHz.

2. IIC overall simulation

Relevant procedures are attached. The following is the simulation waveform.

This paper interprets the FPGA implementation principle and process of IIC bus

Fig. 5 overall simulation waveform of IIC

Combined with the above simulation waveform diagram and program, it can be seen that:

Start bit: SCLK is the high level, SDAT is from high to low, indicating the beginning of IIC bus data transmission;

Then, one byte of data, 4a, is transmitted as the address of the slave, followed by a high level, which is the reply bit;

Then, one byte of data, i.e. 01, is transmitted as the sub address of the slave address, followed by a high level, which is the reply bit;

After that, one byte of data, i.e. 08, is transmitted, which is the data configured for the above sub address register, and then followed by a high level, which is the reply bit;

Finally, it is the stop bit, SCLK is the high level, and SDAT is from low to high, indicating the end of the IIC bus transmission data.

The simulation results show that when a byte is transmitted, the SDAT is the high level of a pulse, rather than pulling the SDAT down and then up from the device, which is also possible.

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