Author: Wilfried platzer, application engineer of ADI company

Question:How to add isolation to ADC without compromising its performance?

answer:For isolated high-performance ADC, on the one hand, pay attention to isolate the clock and on the other hand, pay attention to isolate the power supply.

SAR ADC has traditionally been used in applications with lower sampling rate and lower resolution. Today, there are fast, high-precision, 20 bit SAR ADCs with 1 MSPs sampling rate, such as ltc2378-20, and oversampled SAR ADCs with 32-bit resolution, such as ltc2500-32. When ADC is used in high-performance design, the whole signal chain needs very low noise. When the signal chain requires additional isolation, performance is affected.

With regard to isolation, there are three aspects to consider:

  • Ensure that there is an isolated power supply at the hot end
  • Ensure that the data path is isolated
  • Clock isolation of ADC (sampling clock or conversion signal) to prevent clock generation at the hot end

Isolated power supply (comparison between flyback topology and push-pull topology)

For sensor applications, the isolated power supply is usually in the range of less than 10 W.

Flyback converters are widely used to isolate power supplies. Figure 1 shows the simple and feasible characteristics of flyback converter. The advantage of this topology is that few external components are required. Flyback converter has only one integrated switch. The switch may be the main noise source affecting the performance of the signal chain. For high-performance analog design, flyback converter will bring many breakpoints and cause electromagnetic radiation (called EMI), which may limit the performance of the circuit.


Figure 1. Typical flyback converter topology

Figure 2 shows the current in transformers L1 and L2. In the primary (L1) and secondary (L2) windings, the current jumps from high to zero in a short time. The current spike can be seen in the I (L1) / I (L2) trace of Fig. 3. Current and energy accumulate in the primary inductance. When the switch is disconnected, they are transmitted to the secondary inductance to produce transients. It is necessary to reduce the transients caused by switching noise effect. Therefore, buffers and filters must be inserted in the design. In addition to additional filters, another disadvantage of flyback topology is that the utilization of magnetic materials is low, and the required inductance is high, so the transformer is large. In addition, the thermal loop of flyback converter is also large and difficult to manage. For background information on the thermal loop, see application note an139.

Another challenge for flyback converters involves switching frequency variation. Figure 3 shows the frequency change caused by load change. As shown in Fig. 3a, T1 T2. This means that fswitch changes as the load current decreases from a higher load current I1 to a lower load current I2. The change in frequency will generate internal noise at unpredictable times. In addition, the frequency will also vary from device to device, which makes it more difficult to filter because each PCB needs to adjust the filtering. For a 20 bit SAR ADC with a 5 V input range, 1 LSB phase When about 5 μ 5. The error introduced by EMI noise shall be less than 5 μ 5. This means that flyback topology should not be selected when isolating power supply for precision system.

There are other isolated power structures with low electromagnetic radiation disturbance. In terms of radiation, push-pull converter is more suitable than flyback converter. Push pull regulators such as lt3999 provide the possibility of synchronization with ADC clock, which helps to achieve high performance. Figure 4 shows the synchronization of the lt3999 in the isolated power supply circuit with the ADC sampling clock. Remember that the primary to secondary capacitors provide a return path for switching noise to avoid the effect of common mode noise. The capacitance can be realized in PCB design using overlapping top-level plane and second-level plane, and / or using actual capacitance.


Figure 2. Lt8301 switching current in transformer winding


Figure 3. (a) lt8301 frequency variation, (b) close up of frequency variation from 2.13 MS to 2.23 Ms


Figure 4. Lt3999 with ultra low noise post regulator

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Figure 5. Lt3999 current waveform


Figure 6. Lt3999 and its switching relationship with synchronization pin

Figure 5 shows the current waveform (primary and secondary side currents) at the transformer, which makes better use of the transformer and provides better EMI behavior.

Figure 6 shows the synchronization with the external clock signal. The end of the acquisition phase is aligned with the positive edge of the synchronization pin. Therefore, there will be about 4 μ S longer quiet time. This allows the converter to sample the input signal within this time range and minimize the transient effect of the isolated power supply. The acquisition time of ltc2378-20 is 312ns, which is very suitable for 1 μ S quiet window.

Data isolation

Data isolation can be achieved using digital isolators, such as adumx series digital isolators. These digital isolators can be used for SPI, I2C, can and many other standard interfaces. For example, adum140 can be used for SPI isolation. In order to achieve data isolation, only SPI signals, SPI clock, SDO, SCK and busy need to be connected to the data isolator. In data isolation, electrical energy is transmitted from the primary side to the secondary side through inductive barriers. The current return path needs to be added, which is done by the capacitor. The capacitor can be realized by overlapping planes in PCB.

Clock isolation

Clock isolation is another important task. If a 20 bit high-performance ADC with a 1 MHz sampling rate is used, such as ltc2378-20, a signal-to-noise ratio (SNR) of 104 DB can be achieved. In order to achieve high performance, a jitter free clock is required. Why not use standard isolators like adum14x series? Standard isolators increase clock jitter, limiting ADC performance. See design note dn1013 for more details.

Figure 7 shows the theoretical limit of SNR under different frequencies and different types of clock jitter. The aperture clock jitter of high-performance ADC such as ltc2378 is 4 ps, and the theoretical limit is 106 dB at 200 kHz input.


Figure 7. Relationship between clock jitter and ADC performance


Figure 8. Clock isolation using standard isolators

The standard clock isolator concept shown in Figure 8 includes:

  • A good standard digital isolator like adum250n has a jitter of 70 PS RMS. For 100 dB SNR targets, the signal sampling rate is limited to 20 kHz due to clock jitter.
  • Optimized clock isolators like the ltm2893 provide low jitter of 30 PS RMS. For the 100 dB SNR target, the current signal sampling rate is 50 kHz, which can provide more bandwidth under all SNR performance.


Figure 9. Clock isolation using LVDS clock isolator

  • Figure 9: for higher input frequencies, LVDS isolators should be used. Adn4654 provides 2.6 PS jitter, close to the best performance of ADC. At 100 kHz input, the SNR limit caused by clock jitter will be 110 dB.


Figure 10. Clock isolation using additional PLL to purify clock jitter

  • Figure 10: using PLL to purify the clock. Adf4360-9 can help reduce clock jitter.

Figure 11 shows a more detailed block diagram of using PLL to purify the clock. You can use adf4360-9 as a clock purifier and add a 2 frequency divider at the output. The ad7760 is rated to support 1.1 MHz.


Figure 11. Adf4360-9 used as clock purifier

Therefore, 1 MSPs SAR ADC such as ltc2378 cannot be directly supported. In this case, a low jitter trigger will help. It divides the clock 2.


Figure 12. Trigger used to lower clock for ltc2378


Figure 13. Clock generation on the isolated (hot) side

  • Fig. 13: locally generated clock is another scheme to obtain a clock with the required jitter performance. Local clock generation makes the clock architecture more complex because it introduces the asynchronous clock domain into the system. For example, if two separate isolated ADCs are used, the absolute frequency of the clock will be different, and the sampling rate conversion must be increased to re match the clock. For some details about the sampling rate conversion, please refer to the engineer’s dialogue note ee-268.

Clock design of high performance sigma delta ADC

The similar problem of clock is also applicable to high-performance sigma delta ADC, such as ad7760. Here, an important clock signal is a jitter free oversampling clock, such as 40 MHz. In this case, no additional frequency divider is required.


Isolated high-performance ADC requires careful design of isolation scheme and selection of isolation technology to achieve high-performance SNR higher than 100 dB. Special attention should be paid to isolating the clock, because the impact of clock jitter may damage performance. Secondly, attention should be paid to isolating the power supply. Simple isolated topologies, such as flyback, introduce high EMI transients.

For better performance, push-pull converters should be used. Attention should also be paid to data isolation (although not very important). The available standard devices can provide good performance and have little impact on the overall system performance. The introduction of these three isolation topics will help designers put forward high-performance isolation system solutions.

Introduction to the author

Wilfried platzer studied information technology in Karlsruhe, Germany, focusing on RF technology. He started working at ITT in 1997 and later at TDK Micronas. Wilfried has held various positions, starting with field application engineer, and then focusing on the concept and system architecture engineering design of mixed signal IC. 11 years later, he jumped to AUMA to engage in electronic pre development. In 2015, he joined linglilte (now part of ADI). At present, Wilfried is a senior field application engineer of ADI company, responsible for providing regional support to Switzerland.

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