DRAM module is one of the most electronic equipment modules, we are also familiar with DRAM. But do you really know DRAM? What is the structure of DRAM’s basic unit? How does DRAM work? If you are interested in DRAM, read on.

1、 DRAM introduction

DRAM’s full English name is “dynamic RAM”, translated into Chinese is “dynamic random access memory”. DRAM can only keep the data for a short time. In order to keep the data, DRAM must refresh at intervals. If the storage unit is not refreshed, the data is lost. DRAM is used for general data access. We often say how big the memory is, mainly refers to the capacity of DRAM.

All DRAM basic units consist of a transistor and a capacitor. Take a look at the figure below

The figure above is just a schematic diagram of the basic unit of DRAM: the state of capacitor determines whether the logical state of DRAM unit is 1 or 0, but the feature of capacitor being used is also its disadvantage. A capacitor can store a certain amount of electrons or charge. A charged capacitor is considered a logical 1 in digital electronics, while an empty capacitor is 0. The capacitor can not keep the stored charge for a long time, so the memory needs to be refreshed regularly to keep the temporary data. Capacitors can be charged by a current – of course, this current is limited, otherwise it will break down the capacitor. At the same time, it takes a certain time for the capacitor to charge and discharge. Although the time for the capacitor in the basic unit of memory is very short, only about 0.2-0.18 microseconds, the memory can not be accessed during this period.

According to DRAM manufacturer’s data, the memory should be refreshed at least every 64ms, which means that the memory needs to be refreshed for 1% of the time. The automatic refresh of memory is not a problem for memory manufacturers, but the key is to keep the memory content unchanged when reading the memory unit. Therefore, DRAM unit needs to refresh after each read operation: perform a write back operation, because the read operation will also destroy the charge in the memory, that is to say, the data stored in the memory is damaged Sexual. Therefore, the memory should be refreshed not only every 64ms, but also after each read operation. This increases the cycle of access operations, and of course the longer the latency. SRAM and static RAM have no refresh problem. A SRAM basic unit consists of 4 transistors and 2 resistors. Instead of storing data by using the characteristics of capacitor charging and discharging, it uses the state of the transistor to determine the logic state, which is the same as that in the CPU. Read operations are not destructive to SRAM, so there is no refresh problem with SRAM.

SRAM can not only run at a higher clock frequency than DRAM, but also have a much shorter latency than DRAM. SRAM only needs 2 to 3 clock cycles to access the required data from CPU cache, while DRAM needs 3 to 9 clock cycles (here we ignore the time of signal transmission between CPU, chipset and memory control circuit).

2、 Basic principles

DRAM is composed of transistors and a small capacity f-capacitor storage unit. Each memory cell has a small etch transistor, which keeps the storage state, that is, on and off, through the charge of a small capacitor. Capacitors are similar to small rechargeable batteries. It can be charged with voltage to represent 1, and after discharge it represents 0, but the charged capacitors will lose their charge due to discharge, so they must be continuously “refreshed” by a new charge.

The figure below shows the frame diagram of the standard DRAM structure. Different from SRAM, the address lines of the standard DRAM are divided into two groups to reduce the number of input address pins and improve the packaging efficiency. Although in the standard DRAM structure, the number of input address pins can be reduced by arranging multiple addresses, in this way, the clock control of the standard DRAM memory unit will become more complex, and the running speed will be affected. In order to meet the requirements of high-speed DRAM applications, separate address input pins are generally used to reduce the complexity of clock control and improve the running speed.

DRAM controller provides row address strobe (rowaddress strobe) and column address strobe (CAS) to lock row address and column address. As shown in the figure, the pins of the standard DRAM are:

Address: divided into two groups, row address pin, column address pin;

Address control signal pin: Ras and CAS;

Write permission signal: write;

Data input / output pins;

Power pin.

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