The increasing complexity of system design requires the design of high-performance FPGA and PCB to be carried out in parallel. By integrating FPGA and PCB design tools and adopting advanced manufacturing processes such as high-density interconnection (HDI), this design method can reduce the system cost, optimize the system performance and shorten the design cycle.

Figure 1 FPGA and PCB

The design team must work in parallel and constantly exchange data and information to ensure the success of system design

The driving force behind the electronics industry is the demand for faster and cheaper products and bringing products to market before competitors. The progress of IC technology has always been one of the main factors to promote the increase of function and performance, and FPGA technology has been developing at a very fast speed. Different from the past when FPGA was only used as glue logic, FPGA has been used to realize the main system functions. The number of logic gates of FPGA has reached 10 million, and the core speed has reached 400MHz, which can provide the next generation inter chip communication speed of up to 11gbps. At the same time, it still maintains a very reasonable cost. Therefore, compared with ASIC and custom IC, FPGA is a more attractive choice.

The effect of the progress of IC and FPGA technology on downstream industries has affected the PCB industry. The number of senior executives and high-performance packaging promote the new PCB production and design technology, which has functions such as embedded passive components, thousands of megabits of signal and EMI analysis, and puts forward the demand for special high-density and high-performance wiring. The basic system design method is also changing. The design of FPGA and PCB can be carried out in parallel to reduce the system cost, optimize the system performance and shorten the design cycle.

PCB and FPGA are generally created in different design environments. In the past, these design schemes rarely communicated with each other. However, with the increasing popularity of high-performance and high-density FPGA devices, in order to meet the tight listing schedule, PCB and FPGA design teams must work in parallel (see Figure 1) and constantly exchange data and information to ensure the success of the whole system design.

When implementing high-end FPGA on PCB, design engineers face the dual challenges of performance optimization and system design productivity. The design engineer must ask himself: what is the problem that slows down the process? What needs to be done to get the best performance? The answers to these questions can help them identify solutions that can achieve smaller, cheaper and faster systems.

Design efficiency challenges

When the design engineer needs to design PCB and FPGA in parallel, the FPGA design engineer can no longer design independently as before, and then hand over the completed FPGA design to the PCB design engineer. A competitive design requires FPGA and PCB design engineers to cooperate from top to bottom and make some compromises to ensure an optimal system. The advantage of concurrent design is that it can reduce the design cycle, optimize the system performance and reduce the manufacturing cost.

The challenge of concurrent design is that the results obtained by FPGA layout and wiring tools need to be accurately and quickly mapped to the schematic diagram and PCB layout. At the same time, any change of PCB design must also be updated on FPGA. The traditional design process is to design FPGA first, and then hand them over to PCB design engineers for circuit board implementation. Now this practice is no longer feasible.

If FPGA design / synthesis, layout / wiring and PCB design environment are not integrated, the communication between FPGA and PCB schemes must be realized manually. This may be acceptable for small FPGAs with hundreds of pins, but many designs now have multiple highly complex FPGAs. Using this method for information communication will be very time-consuming and error prone. This problem can be highlighted only by the creation and update of PCB schematic symbols of high-level pin count FPGA.

Another problem involves a large FPGA on a PCB. Different from the symbols of small FPGA, a single symbol of large FPGA cannot be placed in one schematic diagram. These symbols must be divided into several symbols through functional grouping and remain unchanged in the repeated process of FPGA design.

In addition, the I / O allocation of FPGA has also become a systematic problem. Design tools need to be able to manage pin assignments, but they must be used by PCB and FPGA design engineers to communicate pin constraints. PCB design engineers cannot create a condition to prevent FPGA timing convergence, and FPGA design engineers cannot create a condition to prevent system timing convergence.

The examples given in Figure 3 and Figure 4 reflect the wiring before and after the performance optimization of FPGA assembled on PCB. The 32-bit bus of FPGA must communicate directly with the left connector. This is a high-speed bus, and all networks on it must be matched to obtain appropriate skew control.

In Figure 3, in order to match all routing lengths with the longest network, the router adds a lot of serpentine routing. From the perspective of PCB wiring, the result is a mess: there are a lot of additional congestion, too many additional routing, and a bus with suboptimal performance.

Figure 3 wiring diagram before FPGA performance optimization

In Figure 4, the router also matches all routing lengths with the longest routing. Even so, the length of each route is only 1.8 inches, compared with 3.2 inches before. The shorter matching length reduces the bus delay to 320 picoseconds. This performance optimization is the result of the integration of FPGA and PCB design process, which can obtain the ideal FPGA pin diagram.

Figure 4 wiring diagram after FPGA performance optimization

This example illustrates the possible challenges of assembling FPGA on PCB, including: additional congestion requires longer PCB design time to complete wiring; Not the optimal system performance; Additional wiring requires additional PCB layers, which increases manufacturing costs.

Functional performance barriers

IC and FPGA devices have been optimized for higher performance. For example, they can now achieve serial communication performance of gigabytes per second. From the perspective of timing convergence, signal integrity and overall reduction of PCB wiring density, this method has the following advantages:

(1) Timing calibration is not so strict: the clock is contained in the serial signal, so the design engineer does not need to manage the timing between the clock and data;

(2) Improve signal integrity: all signals use differential line pairs, which can improve signal quality;

(3) Wiring simplification: serial signals are transmitted along one path (actually differential line pairs), rather than parallel transmission on a bus with multiple routes, which means that interconnection requires less routes and layers;

(4) On Chip Termination: by integrating variable resistance terminator in FPGA, less surface mount devices are required on the board, which can save space and improve performance. The updated device also includes on-chip capacitance, which can save more space.

The use of these high-end FPGAs in the system makes PCB design the key to the success of the whole system design. The system must be able to run at high speed, have production cost-effectiveness and be designed on time.

The communication speed of several gigabytes per second requires a new set of tools that can route and verify signals. At this time, the wiring, connectors and vias on the PCB also need to consume power. They must be modeled carefully, and the classical signal integrity analysis method is used to calculate the delay, overshoot / undershoot and crosstalk. In addition, the working range of GHz must be modeled and understood with the pre emphasis mode. EDA and FPGA suppliers are also cooperating to provide accurate device models, design constraints and reference designs in the form of “Design Suite”, which will improve the design quality and shorten the design cycle.

Serial I / O also requires improved PCB layout and wiring technology driven by common system constraints. In addition, the routing of differential line pairs must be strictly controlled according to the maximum matching delay and the number of vias used.

Advanced PCB manufacturing technology

Another challenge arising from the number and density of high-end FPGAs is to assemble the FPGAs on the PCB and then connect them to other ICs on the board. There are so many pins in a small area that it is almost impossible to make internal wiring using ordinary PCB manufacturing process. As a result, these devices promote the adoption of advanced PCB manufacturing technologies, such as high-density interconnection (HDI) and embedded passive devices.

HDI uses IC manufacturing technology on PCB. HDI layer deposited on the traditional PCB laminate layer (such as FR4) can produce very narrow routing and small vias (micro vias), and it is easy to fan out away from high-density packaging, usually ball grid array (BGA) or chip level packaging (CSP). In addition, using these HDI technologies also requires special PCB layout software that can understand this mixed PCB and IC production technology.

The benefits of HDI / micro vias include:

Reduce product size: the height and thickness of PCB substrate are reduced, and the volume is also reduced;

Increase the wiring density: each device has more wiring, and the devices are arranged more closely;

Cost reduction: HDI can reduce the number and area of circuit boards, so that each large bare board can produce more circuit boards and reduce production costs;

Improve electrical performance: the parasitic effect of HDI is only one tenth of that of through hole, its lead is shorter and its noise margin is greater;

Reduce radio interference (RFI) / EMI: because the ground plane is closer to or on the surface, the distributed capacitance of the ground plane can be used to greatly reduce RFI / EMI;

Improve heat dissipation efficiency: the insulation medium of HDI layer is very thin and the temperature gradient is very high, which can improve the heat dissipation performance;

Improve design efficiency: Micro vias make the double-sided layout easier, and also improve the routing of device pins (through holes on the pad), thus leaving more inner wiring space;

Improve the yield (DFM): due to the small gap, HDI board hardly needs to be pressed;

Reduce the number of layers: generally, surface mount technology (SMT) of 10 to 12 layers is required, and only 6 layers are required for HDI manufacturing process;

Shorten the design cycle: due to the use of buried holes, the wiring space is more sufficient, which can significantly reduce the design time.

In addition, these high-level pin count devices need a lot of decoupling capacitors and termination resistors to ensure working performance. Traditional SMD passive devices will occupy the valuable area of the surface layer. By embedding these passive components into the inner layer of PCB, the size of PCB can be greatly reduced and the performance can be improved.

Embedded passive components have many advantages, including:

Increase the design density: moving the passive SMD into the inner layer can make other devices arranged more closely;

Reduce system cost: although additional steps will increase production cost, the overall system cost can be reduced by reducing SMD and minimizing circuit board area;

Reduce system weight and circuit board area: removing SMD can reduce the size and weight of circuit board;

Improve performance: passive devices can be very close to active devices, which can reduce inductance and improve performance;

Improve reliability and quality: less SMD to be assembled means less potential welding faults;

Add functionality: create opportunities for adding functionality without worrying about reducing the design area.

Like any other emerging technology, its costs will fall as the underlying technologies that support them evolve. Embedded passive device technology is like this. It was only used in very cutting-edge design, but now it is even used in consumer products that require small size and high function.

The key to the design of embedded passive components is to have automatic tools that are convenient for efficient design. If the library components are defined manually, it is impossible to design hundreds of passive components with different parameter values and tolerances. It requires an automatic synthesis algorithm driven by resistance and capacitance characteristic parameters (from component suppliers). These synthesis algorithms drive the trade-off tools needed to analyze all passive components and help determine the best material combination and overall dimensions. These trade-off tools help to reduce the number of devices on the circuit board and reduce the production steps and final costs.

Summary of this paper

Companies engaged in electronic product design need compact and two-way integration of FPGA tools and PCB design tools, as well as close cooperation between EDA and FPGA suppliers. With this integration and cooperation, they can achieve the goal of time to market and performance,

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