When porting the new version of u-boot, I searched the Internet for information about how to use the power management chip, and found that there was almost no information, even the datasheet was difficult to download. I don’t know why? I can only understand that this part of knowledge is relatively simple, no one is willing to write it. But there is no harm in recording the principle and usage as a memo. In addition, it still needs to be declared in advance that only the configuration method recommended by the official manual is provided here, and the free play method does not guarantee the feasibility and stability.

1、 Overview

Concepts of LDO and Buck: please refer to buck vs LDO in embedded circuits.

S5m8767a has 9-way buck and 28-way LDO, which can be used as a total of 37 power supply circuits. The 37 way power supply circuit can use 6.25 MV step voltage at least, and can control the output voltage accurately with more than 60 voltage levels. In addition, the s5m8767a also has a hardware RTC, which can save the clock information in the case of external battery power supply.

2、 The relationship between PMIC and uboot

Uboot initializes the hardware according to the module and has its own code sequence, which requires PMIC to provide power to specific hardware in advance at a specific time point for uboot to initialize and configure. Otherwise, the execution of uboot is bound to fail. For example, PMIC needs to supply power to its two power supplies before EMMC initialization.

In addition, the initialization time of PMIC has its default time point in uboot, but this time point is closely related to the actual circuit of the core board and backplane, which needs to be advanced or delayed according to the actual needs.

2.0 classification of Buck and LDO in PMIC

Buck and LDO in PMIC can be divided into two types

One is buck and LDO which can output voltage directly when PMIC is powered on.

The other is buck and LDO, which can only output voltage after PMIC is configured with I2C.

2.1 relationship between PMIC and DDR

For 4412, DDR initialization is carried out in BL2. At this time, if the assembly initialization hardware I2C is used to configure the PMIC, I don’t think it’s meaningful. Therefore, the DDR power supply needs to be connected to the default on buck of PMIC, that is, the buck that PMIC can directly output voltage when it is powered on, without code configuration.

S5m8767a recommends using buck5 as the power supply of DDR,

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However, the default output of buck5 is 1.2V, and DDR needs standard 1.5V. What’s the problem?

Samsung has considered this problem for us for a long time. In order to adapt to different types of DDR, buck5 can output four default voltages through the level matching of K9 K10 pins

Here, the development board of Xunwei is set as follows:

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In this way, b5s1: b5s2 = 1:0, that is, buck5 outputs 1.5V voltage, which is just in line with the demand of DDR.

2.2 relationship between PMIC and 4412 main chip

The voltage supplied to the arm core is buck2 of PMIC, which is also on by default, with a default output of 1.1V. After consulting the 4412 spec, it should be noted that at 1.1V, the APLL that provides the clock for the arm core can only output 1000MHz at most, that is, if PMIC is not set at the beginning of power on, the arm core can only work at 1000MHz, and can not use the maximum frequency of 1.4GHz.

3、 Setting method of PMIC

3.1 communication protocol

S5m8767a uses I2C protocol to communicate with 4412. The slave address is divided into two parts, PM (power manager) and RTC. That is to say, the register addresses of PM and RTC are separated, which can be regarded as two separate chips.

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3.2 examples

Take buck1 as an example to illustrate the register setting method. Other bucks are basically similar to LDO. If necessary, read the manual carefully

Buck1 has two 8-bit control registers,

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The lower 6 bits of ctrl1 can be set according to the default value. The higher 2 bits need to be explained. The meanings of 00 and 1x don’t need to be explained. The meaning of 01 is The switch of buck1 is controlled by the external pin of pwren, which is generally connected with the xpwrrgton pin of 4412. The xpwrrgton is automatically controlled by the CPU. When the CPU is in the sleep state, the pin is low and the pin in the working state is high. That is to say, once the CPU exits the sleep state, the PMIC will power up all buck & LDO controlled by pwren.

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Ctrl2 is to control the output voltage of buck2, the step value of 6.25mv, how much voltage you need to calculate and then write.

4、 Using PMIC technology of experts

Originally published in: what is PMU

What is PMU (PMIC)

PMU(power management The power management unit (PMU) is a highly integrated power management solution for portable applications, that is, several kinds of traditional discrete power management chips, such as low dropout linear regulator (LDO) and DC / DC converter (DC / DC), are now integrated into the power management unit (PMU) of mobile phones, which can achieve higher power conversion efficiency and lower cost Power consumption, and fewer components to adapt to the reduced board level space, lower cost.

As a power management integrated unit for specific main chips of consumer electronics (mobile phone, MP4, GPS, PDA, etc.), PMU can provide all kinds of multi-level power supplies with different voltages required by the main chip. The same voltage energy supplies different mobile phone working units, such as processors, RF devices, camera modules, etc., so that these units can work normally. According to the needs of the main chip, the power management, charging control and on-off control circuit are integrated. Including adaptive USB compatible PWM charger, multi-channel DC-DC converter, multi-channel linear regulator (LDO), charge pump, RTC circuit, motor drive circuit, LCD backlight drive circuit, keyboard backlight drive circuit, keyboard controller, voltage / current / temperature, multi-channel 12 bit ADC, and multi-channel configurable GPIO. In addition, over / under voltage (OVP / UVP), over temperature (OTP) and over current (OCP) protection circuits are integrated. Advanced PMU can distribute power safely and transparently between USB and external AC adapter, lithium battery and application system load. Dynamic power path management (DPPM) shares AC adapter current between system and battery charging, and automatically reduces charging current when system load rises. When charging through the USB port, if the input voltage falls below the threshold to prevent the USB port from collapsing, the input voltage based dynamic power management (IDPM) will reduce the input current. The power path architecture also allows the battery to compensate for such system current requirements when the adapter is unable to provide peak system current.

LDO is a kind of voltage stabilizing device which can adjust the output voltage through negative feedback to keep it constant by using low working voltage difference. LDO is used when the pressure difference is small, with turn off function, which is convenient for power management. DC-DC is more efficient than DC-DC.

According to the needs of the system, the power supply can provide a variety of voltages, which are required for voltage adjustment. In addition, the power supply can simultaneously turn on and off these supply voltages with the function to support voltage domain switching.

PMU is usually customized with the main chip. Because it needs to match the power on timing of CPU. The power on sequence and time interval of some voltages have sequence relation and time requirement. This is a mask okay. PMU is a special power controller with mask program. It needs 32.768KHz crystal and 19.2m crystal. The standby mode is 32.768KHz and the normal mode is 19.2m.

After the battery is put on, the PMIC enters the standby mode. The PMU is provided with a clock by a 32.768KHz crystal. After the power button is pressed to trigger the start-up, the corresponding LDO and DC-DC are turned on according to the customized start-up sequence. The 19.2m master clock works. After the CPU power supply is normal, the output is set to the CPU, the reset signal is output to the CPU, and the reset signal is released, and the CPU starts to start. CPU output PS_ The hold signal puts the state of PMIC in working state. (the CPU will turn off the PS when the power is off_ Hold power down, PMIC shut down and enter shutdown state)

After the CPU works normally, each module of PMIC can be controlled through I2C interface. For example, when the system frequency conversion, different working frequency to adjust the core voltage to the corresponding voltage. RTC time setting and alarm clock. At the same time, PMIC can send the interrupt signal generated by the abnormal event to the CPU, and then the CPU can process the interrupt.

The more the power supply of PMIC, the finer the power supply to the modules of the system, and the less the power supply of each module is involved, so the more power is saved.

reference material:

[1] SEC_ S5M8767A01-6070_ Data Sheet_ Ver.0.10.00_ Preliminary.pdf

[2] DS_ K4B2G1646Q-BC_ Rev103.pdf

[3] SEC_ Exynos 4412 SCP.pdf

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