1. Introduction

Charge coupled device (CCD) It is a new semiconductor device that appeared in the late 1960s. At present, with the continuous improvement of the performance of CCD device, it is increasingly widely used in the fields of image sensing, size measurement, positioning measurement and control. The front-end driving circuit of CCD application is expensive, and the performance index is restricted by the manufacturer’s technology and process level. It brings great inconvenience to users. There are two kinds of CCD drivers One is that the CCD device outputs the analog signal under the action of pulse, which is amplified by the back-end gain adjustment circuit for voltage or power, and then sent to the user; the other is that on this basis, it also includes the part that digitizes its analog quantity according to a certain output format, and then transmits the digital information to the user. The general linear CCD camera refers to the latter, plus a mechanical scanning device Therefore, according to the requirements of different application fields and technical indexes, selecting different types of linear CCD devices and designing convenient and flexible driving circuit to match them is one of the key technologies in CCD application.

This paper takes tcd1501c CCD image sensor as an example. The performance parameters and the design of peripheral driving circuit are introduced. The driving timing parameters can be flexibly set through VHDL program. The circuit has been successfully developed and applied to a non-contact position measurement product.

2. Working principle of CCD

CCD takes charge as signal, which is different from most other devices. It takes current or voltage as signal. Its basic function is the generation, storage, transmission and detection of signal charge. When light is incident on the photosensitive surface of CCD, CCD first completes photoelectric conversion. That is, an optical charge linearly related to the amount of incident light radiation is generated. The working principle of CCD is that the subject reflects light onto the CCD device. CCD accumulates corresponding charges according to the intensity of light. A weak voltage signal proportional to the amount of light charge is generated, filtered and amplified, and an electrical signal or standard video signal that can represent the light intensity of sensitive objects is output through the driving circuit. Based on the above principle of transforming one-dimensional optical information into electrical information output, linear CCD can realize the functions of image sensing and size measurement. Figure 1 shows the CCD spectral response curve.

The principle, performance characteristics and driving circuit design of tcd1501c CCD image sensor

3. Implementation of driving circuit

The main technical indexes of linear CCD tcd1501c are as follows: the number of image sensing units is 5000; The pixel size is 7 μ m × seven μ m; The pixel center distance is 7 μ m; The total length of pixels is 35 mm; The spectral response range is 400 NM-1000 nm. The peak wavelength of spectral response is 550 nm and the sensitivity is 10.4 V / LX. S ~ 15.6 V / LX. S. The driving circuit of CCD chip has two main functions. One is to generate multi-channel timing pulses required for CCD operation. The second is to process the original analog signal output by CCD, including gain amplification and conversion from differential signal to single ended signal. Finally, the driver outputs the analog or video information required by the user.

3.1 design of driving sequence based on VHDL

This part of the design is based on Xilinx’s CPLD xc9572-pc44-10 and developed under ise6.1 environment. CCD devices need complex three-phase or four overlapping driving pulses. Most area array CCD are three-phase or four-phase driven, and most linear array CCD are two-phase driven. Taking the two-phase linear array CCD image sensor tcd1501c as an example, the driving circuit design completed by CPLD is realized in this paper. CCD is a capacitive load and has certain power consumption at high working frequency. Therefore, it is necessary to reset pulse RS, shift pulse (also known as optical integration pulse) sh, clamp pulse CP, acquisition and protection pulse SP and two-phase clock pulse output by CPLD Φ 1E、 Φ Each drive pulse such as 2E is shaped and amplified by 74hc14. Then it is sent to the corresponding input of tcd1501c device, and the signal 0s and compensation signal DOS will be obtained at the analog signal output of CCD. The typical optimal operating frequency of tcd1501c is 1MHz. The device has 5000 effective pixel outputs. When tcdl501c works normally, 76 dummy pixels are output. A scan line cycle shall contain at least 5076 clock pulses, i.e. TSH 5076 ×Φ 1E 0.1 μ s. In this design, TSH = 5200 ×Φ 1E。 It can be seen that changing the clock pulse frequency or increasing the number of clock pulses in the optical integration pulse cycle can change the optical integration cycle, usually Φ The frequency of 1E is set to be adjustable, so that the advantages of CCD device can be flexibly used to change the optical integration time according to the actual application environment of CCD device. As long as conditions permit, in order to reduce the charge transfer loss rate of CCD. The frequency of CCD driving pulse shall be as small as possible. When the frequency of the driving pulse decreases, it can be observed that the amplitude of the CCD output signal increases significantly on the oscilloscope. Figure 2 shows the working waveform of CCD.

CCD working waveform

The following is the VHDL program for generating timing pulses:

VHDL program for generating timing pulses

VHDL program for generating timing pulses

VHDL program for generating timing pulses

VHDL program for generating timing pulses

3.2 differential driving design of CCD output signal based on AD623

Under the action of driving pulse, CCD sequentially outputs video signal through shift register. Every time reset pulse RS is reset, CCD outputs an optical pulse signal. Because tcd1501c signal detection adopts gated charge integrator structure. The video output signal is superimposed with some crosstalk signals caused by the periodic reset signal rs. And the effective signal amplitude is small, about 500 MV. The DC voltage is about 4.1V. This is a group of typical differential signals with high common mode voltage and low effective differential mode signal. The signal waveform is shown in Fig. 3 and Fig. 4. Therefore, before subsequent processing (including long-line transmission, a / D conversion, etc.) of analog signal output, a series of preprocessing shall be carried out to eliminate reset pulse crosstalk and other interference in video signal, and amplify the amplitude and driving ability of weak video signal. Because it is the processing of differential signal, we first discuss the basic concept of differential circuit. Figure 5 shows the schematic diagram of differential mode and common mode voltage in differential signal measurement circuit. Vdiff is the signal differential mode voltage, VCM is the signal common mode voltage, and the signal output Vout = R2 / R1 · vdiff = g · vdiff. Under ideal conditions, the general differential mode gain G ≥ 1, while the common mode gain (% mismatch / 100) × G / (G + 1) is close to zero, so it can be seen that the common mode gain is mainly a function of resistance mismatch. In the actual measurement circuit, the common mode voltage at the two inputs may be inconsistent due to the small mismatch of resistance value, so that the DC common mode gain of the circuit is not zero. Common mode rejection ratio (CMRR) is the ratio of differential mode gain G to common mode gain. Expressed in logarithmic form: 201g [(100 /% mismatch) × (G+1)]。 In practical engineering applications, the circuit works in a large noise source. For example, the noise of 50 Hz AC power line, the switching noise of equipment and the transmission noise of wireless signal. These interference signals act on the differential input and will generate a common mode signal at the output. Therefore, differential signal processing requires not only high DC CMRR, but also high AC CMRR.

In the circuit design, the instrument amplifier AD623 of ADI company is selected. The internal structure principle is shown in Figure 6.

Signal waveform

Schematic diagram of differential mode and common mode voltage in differential signal measurement circuit

Internal structure principle

AD623 integrates 3-way operational amplifier. It can work with single or dual power supplies, with high CMRR and very low voltage drift. Except for an external resistance to control programmable gain, all components are integrated internally, which improves the temperature stability and reliability of the circuit. The CCD analog signal processing circuit using AD623 is shown in Figure 7. The video signal and its compensation output are sent to the inverting and in-phase inputs of AD623 respectively. The output terminal of AD623 is connected with a primary emitter follower to enhance the driving ability of the signal. The device can eliminate the temperature drift of output signal caused by common operational amplifier and peripheral resistance.

4. Conclusion

The linear CCD driver based on the above development has been debugged successfully. It is used in a position measurement system and works stably and reliably. As long as the AD conversion part is further expanded, this design scheme can be applied to the front end of the imaging system.

Responsible editor: GT

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