The influence of load capacitance (IO capacitance) Cin on the rising edge of the signal

Any chip IO has input capacitance, usually about 2pf, plus parasitic capacitance, about 3ps. This capacitor is equivalent to the load capacitor. The high-speed signal builds a voltage on this capacitor, which is equivalent to charging the capacitor. The charging formula for the capacitor is:

V0 is the initial voltage of the capacitor, the voltage value after Vu is fully charged, assuming V0=0V. Then the above formula simplifies to:

When t = RC, Vt = 0.63Vu;

When t = 2RC, Vt = 0.86Vu;

When t = 3RC, Vt = 0.95Vu;

When t = 4RC, Vt = 0.98Vu;

When t = 5RC, Vt = 0.99Vu;

The time constant τe we usually use refers to the time it takes for the voltage across the capacitor to rise from 0V to 1-1/e=1-37%=63% (e=2.71828);

Using the above formula, the time required to calculate the rise time from 10% to 90% is:

If the transmission line impedance is 50Ω and Cin=3pf, then τ10-90=0.33ns. If the rise time of the signal is less than 0.33ns, the charging and discharging effect of the capacitor will affect the rise time of the signal. If the rise time of the signal is greater than 0.33ns, this capacitor will increase the rise time of the signal by more than 0.33ns

The direct effect of the load capacitance on the rising edge of the signal is to prolong the rise time, as shown in the following figure:

Influence of capacitive load in the middle of the line on the signal

Test pads, vias, package leads, or short stubs connected to interconnects have parasitic capacitances, equivalent to capacitive loads. These capacitive loads are usually pf level.

Suppose these capacitive loads cause the impedance to jump to 25Ω, which causes the signal to travel here, with the negative signal reflected, and then the incident signal decreases. When the signal reaches the load terminal and returns, at this point, there is a negative signal back to the load terminal. From the waveform point of view, the signal amplitude decreases, undershoots, rings, and the rise time increases.

Let’s calculate the impedance of the load capacitor in the middle of the line:

Assume that the rising edge is linear dV/dt=V/Tr;

If C is small, Zcap is large, and if it is much larger than 50Ω, then in parallel with the impedance of the transmission line, it hardly affects the entire transmission line impedance. If the value of Zcap is comparable to the transmission line, it is 50Ω in parallel with the transmission line, forming an impedance less than 50Ω, which can cause signal integrity problems.

The rule of thumb is that Zcap > 5×50Ω, it will not cause signal integrity issues. Bring in the above formula:

That is:

Assuming the rise time is 1nf, the allowable capacitance is 4pf; if the rise time is 0.25ns, the allowable capacitance is 1pf.

There is an empirical formula for the effect of capacitive mutation on signal rise time:

For a 50Ω transmission line, for a 2pf capacitive abrupt change, the 10-90% rise time of the transmitted signal increases by about 50x2pf=100ps. The delay accumulation of the 50% threshold is about 0.5x50x2pf=50ps.

The delay of the 50% threshold becomes the delay accumulation, and it is more accurate to use this to measure the impact of sudden changes in capacitance on the delay. The above empirical formula is relatively accurate, and the following is the simulation result, which basically agrees:

In order to reduce the influence of sudden change of capacitance on the rising edge of the signal, if the capacitance cannot be reduced, the impedance of the transmission line can only be reduced.

Reviewing Editor: Li Qian