The circuit here is an oscillator with an unusual frequency divider designed by me when developing the RF system. I need a stable and accurate 455khz digital signal generator with as few components as possible. The signal generator must also have a duty cycle of or very close to 50% to eliminate or minimize the second harmonic content.

I first studied the oscillator based on 455khz ceramic resonator and 455khz ceramic filter. However, I need the 442khz signal when I test. But I have a 4.096mhz quartz crystal on hand. By making it oscillate in a stable manner of about 4.095mhz and dividing the frequency by 9 with a 50% duty cycle output, I got the result I wanted.

The design is shown in Figure 1. In addition to the crystal, two integrated circuits and some capacitors and resistors are used. It realizes a pierce oscillator with exclusive OR gate (IC1) as active element. The XOR gate used as an inverter is not the most commonly used gate for this type of oscillator, but three of them are not used in my system, so I tried. The oscillator operates reliably and accurately in this configuration.

The crystal used is of parallel type and is used for 20pF load. I achieved 4.0954mhz by using 100pF for C2 and C3. This frequency is divided by 9 to get 455.04khz, which is enough to meet my design needs.

DI5621_ F1. png? w=950&resize=950%2C545

Figure 1 this design uses a pierce oscillator based on XOR gate and generates a frequency of 455khz with a duty cycle of 50%.

The second IC (IC2) is a 74hc4017, a Johnson counter. I use its output line (pin 12) as the circuit output and configure it to be triggered by the rising edge. The reset input (pin 15) remains at logic level 0. When the state of the counter is between 0 and 4, the carry output line (pin 12) adopts level 1. If its state is between 5 and 9, it adopts level 0.

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You may think that one option of this circuit is to connect Q9 (pin 11) to the reset input. However, in this case, although the frequency output will be 4.0954mhz divided by 9, the output duty cycle will be 55.56% (44.44% if the output is reversed). This can not meet the need to reduce or eliminate the output second harmonic.

To find a duty cycle close to 50%, I added an XOR gate ic1b connected to the output of counter Q4 (pin 10). With this change, the counter will now trigger on the rising edge of the input when Q4 is level 0 and on the falling edge when Q4 is level 1. Therefore, the circuit outputs level 1 of four clock pulses plus the time in the clock, and the fifth pulse indicates that the input is at level 1. When the fifth pulse becomes level 0, the output becomes level 0 and remains unchanged for the next four pulses. Therefore, the input frequency is divided by 9. If the input duty cycle is 50%, the output will also be 50%.

If the input frequency is not 50%, the output will also be turned off, but not so much. The input and output duty cycles are related by the following formula:

DC% output = (400 + DC% input) / 9

Where DC% out and DC% in are the duty cycle of output and input respectively, expressed as a percentage between 0% and 100%. Therefore, if DC% in is between 0% and 100%, the output duty cycle will be between 44.44% and 55.56%, which will not be worse than what I mentioned above.

The circuit test produces an oscilloscope capture as shown in Figure 2. The duty cycle of 4.0954mhz oscillator signal (bottom) and 455.04khz output signal (top) is 50%.

DI5621_ F2. png? w=568&resize=568%2C517

The test results in Figure 2 show that both the input signal and 9 frequency division output have a duty cycle of 50%.

Another XOR gate can be used to make a seven frequency division circuit, as shown in Figure 3. If the duty cycle input is 50%, this will also produce a 50% duty cycle output.

DI5621_ F3. png? w=950&resize=950%2C666

Figure 3 adds another XOR gate to allow the circuit to provide a 7-division frequency of 50% duty cycle output.


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