The following factors need to be considered in the design of GTP signal PCB for FPGA

The GTP performance of spartan-6 FPGA depends on the signal integrity of PCB. The following factors need to be considered in the PCB design process: board laminated structure, component layout and signal routing.

Power supply and stack

For the GTP translator of spartan-6 FPGA, the stack can be divided into two groups: power distribution layer and signal routing layer. The power layer is used to connect the mgtacc, mgtavccpll, mgtavtttx and mgtavttrx power pins of GTP. The laminated structure can be referred to the figure below.

In the stack in the figure above, the ground plane layer transmission signal line provides a signal return path. At the same time, because there is a shielded plane between the two signal layers, the problems to be considered in the routing of adjacent layers can be ignored when routing the signal, and more signal paths are provided.

The power supply layer of GTP shall be closely adjacent to the ground plane to increase the coupling effect. The ground plane can provide shielding for the power supply plane of GTP and shield the noise interference caused by the signal from the upper layer or the lower layer.

In fact, from another point of view, that is, when the noise of the power supply appears in the high-frequency range, with the increase of frequency, it is more and more difficult to find the capacitor, which can cover this frequency range and achieve the filtering effect, until it is impossible to find such a capacitor. With the decrease of capacitance, the related stray inductance and package resistance do not change accordingly, so the frequency response will not change much. In order to achieve better power distribution at high speed, we need to use the power layer and stratum to construct our own capacitance. In order to achieve our purpose more effectively, we usually need to use adjacent power layers and strata.

The connection between the power pin of GTP and the power distribution network plays a key role in the working performance of GTP. PDN and FPGA need low impedance and low noise connection. The FPGA can use a small power supply with a maximum noise of 10MHz to 10MHz. This small power plane should not cover the area of selectio interface.

Capacitor placement

In addition to considering the capacitance value of bypass capacitance, another important aspect to be considered is the placement of capacitance.

The general rule is that the larger the capacitance, the less stringent the placement requirements. If the capacitance value is small, the capacitance should be as close to the pins of power supply and ground as possible. One method that can be adopted is to remove the wiring and vias of the unused general IO, so as to make room for the bypass capacitor. The position of the power division area of GTP and the position of GTP filter capacitor can also be referred to the figure below.

The following factors need to be considered in the design of GTP signal PCB for FPGA

Signal routing

GTP signal routing and selectio signal routing should be avoided in adjacent layers, and their respective return paths should also be separated, including vias.

It is important to keep a certain distance between differential line pairs and between differential lines and other lines. The general rule is that the distance between adjacent line pairs should be at least 5 times the distance between the two lines in the line pair, as shown in the figure below.

The following factors need to be considered in the design of GTP signal PCB for FPGA

Gigabit signal differential lines should avoid changing the routing layer as much as possible. If cross layer transmission is necessary, you need to be very careful. First, you must provide a complete return path. Therefore, we must couple the reference layer of layer a with the reference layer of layer B. Ideally, both reference layers are strata. In this case, the return path can be realized by placing another via connecting two reference layers near the layer transfer via. The following figure shows a schematic diagram of this technology.

The following factors need to be considered in the design of GTP signal PCB for FPGA

If the reference layer is different (one is the stratum and the other is the power layer), place 0.01 as close as possible to the via μ F capacitance to connect the two reference layers to reduce the impedance of the return path. As shown in the figure below.

The following factors need to be considered in the design of GTP signal PCB for FPGA

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