With the increasing scale of modern hardware design, the function of a single program becomes more and more complex. When multiple programs with complex functions are integrated into one FPGA, the structure of FPGA control module is bloated due to the possible conflict between the data path of each program and the occupied resources, which affects the work efficiency of the whole system. Through the multiple configuration of FPGA, the design of control structure can be effectively simplified, and the program that needs a lot of resources can be realized with FPGA devices with less logic resources. Based on virtex5 series development board and configuration memory SPI flash, this paper analyzes the multi configuration from two aspects of hardware circuit and software design, and gives the specific steps to realize the multi configuration, which has a certain reference value for the realization of complex hardware design engineering.

When the FPGA automatically loads the initialized bit stream after power on, it can trigger multiple start events inside the FPGA to make the FPGA automatically download a new bit stream from the address specified by the external configuration memory (SPI flash) to reconfigure. Multiple configuration of FPGA can be realized in many ways.

The design of FPGA multi configuration hardware circuit

  Circuit principle:The hardware of multi configuration mainly includes FPGA board and flash chip which stores configuration files. Ml507 in Virtex-5 series of Xilinx company is selected as FPGA. The product adds special internal loading logic for FPGA multi configuration. Flash chip adopts Xilinx’s SPI flash chip m25p32, which has a storage space of 32 MB. The number of stored files is related to the file size and the FPGA chip used. In order to realize multi configuration, FPGA and external configuration memory should be connected to load configuration file from SPI flash. The hardware connection block diagram of configuration circuit is shown in Figure 1. In FPGA configuration mode, M2, M1 and M0 are 0, 0 and 1. This configuration mode corresponds to boundary scan and pull-up. In this mode, all I / O of FPGA are only valid during configuration. After the configuration, the unused I / O will be floated. The three selection switches m2, M1 and M0 correspond to the 4, 5 and 6 bits of the SW3 switch on the ml507 development board. Set the above switches to 0, 0 and 1 before the FPGA is powered on.

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