Programmable logic device (PLD) is an epoch-making new logic device developed on the basis of ASIC design in the 1970s. Since the advent of PLD devices, TTL, CMOS, ECL and static RAM technologies have been used in the manufacturing process. The device types include PROM, EPROM, E2PROM, FPLA, PAL, GAL, PML and LCA. The development of PLD in performance and scale mainly depends on the continuous improvement of the manufacturing process. High-density PLD is the product of the highly developed VLSI integration process. In the late 1980s, American ALTERA and XILINX companies used EECMOS technology to launch large-scale and ultra-large-scale complex programmable logic devices (CPLDs) and field programmable gate array devices (FPGAs). While this chip achieves high integration, its application flexibility and multi-configuration functions are unmatched by previous LSI/VLSI circuits. Since entering the 1990s, programmable logic device CPLD/FPGA has developed rapidly, moving towards high integration, high speed and low price; not only has the characteristics of electrical erasure, but also edge scanning and online programming have appeared. Advanced features; its application fields are constantly expanding, and can be used in many aspects such as state machines, synchronization, decoding, decoding, counting, bus interface, serial-to-parallel conversion, etc., and applications in the field of signal processing are also active. Using CPLDs can improve system integration, reduce noise, enhance system reliability, and reduce costs.

This article mainly introduces the characteristics and application of Atmel’s CPLD chip ATF1508AS. ATF1508AS is a high-performance, high-density complex programmable logic device (CPLD) realized by ATMEL’s mature electrical erasing technology. It is fully pin-compatible with ALTERA’s EPM7000 series; it can convert the POF file of EPM7000 into an industrial format suitable for ATF1508AS. Standard JEDEC programming files, downloaded to the ATF1508AS chip.

1. Features of ATF1508AS

Each of the 128 macrocells generates a hidden feedback loop to the global bus, and every input pin, I/O pin also feeds into the global bus. The switch matrix of each logic block selects 40 independent signals from the global bus, and each macrocell also generates a return logic item to the local bus. Cascaded logic between macrocells can quickly and efficiently implement complex logic functions. The ATF1508AS includes eight such logic chains, each capable of summing logic terms by fanning in up to 40 product terms.

The ATF1508AS is an in-system programming (ISP) device. It uses an industry-standard 4-pin JTAG interface (IEEE Standard 1149.1) and is fully compatible with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board; in addition to simplifying the production process, ISP also allows design modifications through software.

The pin hold circuit of the ATF1508AS provides settings for all input and I/O pins. When any pin is driven high or low immediately after the pin is left floating, the pin will remain in the previous high or low state. This circuit prevents unused input and I/O lines from floating to intermediate voltage levels, which can lead to unnecessary power consumption and system noise. Pin hold circuitry removes the need for external pull-up resistors and DC power dissipation.

The encryption feature of ATF1508AS can protect the design content of ATF1508AS. The user signal of two bytes (16 bits) can be accessed by the user, and can store the project name, part number, version or date, etc., and the access of the user signal is not affected by the state of the encryption fuse.

The ATF1508AS has a power-on reset feature. During power-up, all I/O pins will be tri-stated until VCC reaches the power-up voltage, which prevents bus contention during power-up. The registers of ATF1508AS are designed to be reset at power-on. After a slight delay from VCC to VRST, all registers will be reset to low level, and the output state should be set according to the polarity of the buffer. This feature is critical for the initialization of the state machine.

2. Macrocell of ATF1508AS

The macro cell of ATF1508AS is shown in Figure 1. Its macrocells are flexible enough to support highly complex logic functions and operate at high speeds. The macrocell consists of five parts: product term and product term selection multiplexer, OR/XOR/cascade logic, flip-flop, output select and enable, logic array input. Unused macrocells can be disabled by the compiler to reduce power consumption.

(1) Product term and product term selection matrix

Each macrocell has 5 product terms, each product term receives as its input all signals from the global bus and the local bus. The product term selection matrix (PTMUX) assigns the five product terms to the logic gates of the macrocell as needed, and is also responsible for assigning control signals. The programming of the product term selection matrix is ​​determined by the design compiler, which will select the optimized macrocell configuration.

(2) OR/XOR/Cascade logic

The logic structure of ATF1508AS is designed to support all logic efficiently. Within a macrocell, all product terms can be OR gated to produce a 5-input AND/OR sum term. By fanning in additional product terms through adjacent macrocells, it is possible to expand to 40 product terms with very little delay. The XOR gate of the macrocell allows efficient implementation of comparison and arithmetic functions, where one input to the XOR gate comes from the summation term of the OR operation, and the other input can be a product term or a fixed high or low level. For combinatorial logic outputs, fixed levels allow polarity selection; for sequential logic, fixed levels allow the use of inversion rules (a corollary of Morgan’s law) to simplify product terms. XOR gates can also be used to simulate T-type and JK-type flip-flops.

(3) Trigger

The flip-flop of ATF1508AS has very flexible data and control functions. The input to the flip-flop can come from an XOR gate, a separate product term, or directly from an I/O port. Selecting individual product terms allows a hidden register feedback to be generated within a combinatorial logic output macrocell (this feature is automatically implemented by the fitter software). In addition to D, T, JK and SR types, the flip-flops of the ATF1508AS can be configured as latches. In this mode, when the clock is high, the data is passed through; when the clock is low, the data is latched.

The clock signal can be the global CLK signal (GCK) and a separate product term. Flip-flops change state on the rising edge of the clock. When the GCK signal is used as the clock signal, a product term of the macrocell can be selected as the clock enable signal. When using the clock enable function, all clock edges will be ignored while the enable signal (product term) is low. The asynchronous reset signal (AR) of the flip-flop can be the global reset signal (GCLEAR), a product term, or not used. AR can also be the logical OR output of GCLEAR and a product term. The Asynchronous Set Signal (AP) can be a product term or not used.

(4) Output selection and enable

The output of the ATF1508AS macrocell can be selected as register type and combination type. Hidden feedback signals can be combinatorial or register signals regardless of whether the output is combinatorial or register. The output enable multiplexer (MOE) controls the output enable signal. For simple output operations, any buffer can be permanently enabled. The buffer can also be permanently disabled if the pin is used as an input. In this configuration, all macrocell resources are still available, including hidden feedback signals, expanders, and cascade logic. The output enable signal of each macrocell can select a global output enable signal. The device has 6 global output enable signals (OE).

(5) Logic array input

Logic array inputs include global bus/switch matrix and return bus:

Global Bus/Switch Matrix

The global bus includes all input and I/O pin signals and hidden feedback signals for all 128 macrocells. The switch matrix of each logic block has all the signals of the global bus as its inputs. Under software control, up to 40 of these signals can be selected as inputs to the logic block.

return bus

Each macrocell can generate a return product term. This signal is connected to the local bus and is valid for 16 macrocells. It is the inverse polarity of a product term for the macrocells. The 16 loopback terms per local bus allow high fan-in summation terms (up to 21 product terms) with minimal delay.

3. Design software support

ATMEL company provides CPLD design software, and many third-party tool software also supports the design of ATF1508AS, which can use a variety of high-level description languages ​​and formats for logic description, such as CUPL, ABEL, VHDL and so on. Since ATF1508AS is fully pin-compatible with ALTERA’s EPM7000 series, ALTERA’s MAXPLUSII software can be used. It can compile and synthesize VHDL language, easy to use and powerful. After MAXPLUSII is synthesized, a POF file suitable for CPLD programming of ALTERA is generated. Using POF2JED software (provided by ATMEL), the POF file can be converted into an industry standard JEDEC programming file suitable for ATF1508AS, and downloaded to the ATF1508AS chip.

4. Device programming

The ATF1508AS device is programmed in-system (ISP) using the 4-pin JTAG protocol. ATMEL provides ISP hardware (download cable) and software to allow programming of the ATF1508AS from a PC. To allow ISP programming to support “Automated Test Facility (ATE)” vectors, Serial Vector Format (SVF) files must be generated by ATMEL’s ISP software, and can also be converted to other ATE test formats other than SVF. The ATF1508AS device can also be programmed with standard third-party programmers, in which case the JTAG ISP port can be disabled to allow the four additional I/O pins to be used for logic functions.

Another feature of the ATF1508AS is that if the programming process is interrupted for any reason, the device will be locked to prevent the input and I/O pins from being driven. In this state, the input and I/O pins default to a high-impedance state. When programming the device, the input and I/O pins will also be in a high-impedance state. Additionally, the pin hold circuit settings will hold their previous state during device programming. The ATF1508AS device is factory-initialized in an erased state and can be used directly for ISP programming.

concluding remarks

The advantages of CPLD devices lie in shortening the development and production cycle, good on-site flexibility, and with the development of electronic technology, its integration level is getting higher and higher, the speed is getting faster and the price is gradually decreasing, so the market is developing rapidly. ATF1508AS of ATMEL Company is a complex programmable logic device with high performance and high density. It is easy to use and has high cost performance, so it has broad application prospects.

Responsible editor: gt

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