Pulse power technology is a kind of power compression technology, which stores energy slowly with low input power, and then releases it in a very short time to obtain high peak output power. This technology is a new science and technology developed in response to the needs of national defense science and technology. It is an important means to obtain extreme electromagnetic parameters such as high voltage and large current. It is widely used in many fields such as scientific research and industrial production.
It consists of a general energy storage system, a pulse energy storage system and a primary pulse power switching system. When working, the primary energy system is used to supply energy to the pulse power device and transfer the energy to the intermediate energy storage system; the common far repetition frequency or burst pulse power device in the intermediate energy storage system is compressed into the pulse forming system for energy supply; after the charging of the pulse forming system is completed, the energy is quickly transferred to the load system through the switch conversion system to realize the pulse power output 。
Burst pulse is a kind of pulse power technology developed to meet the specific industrial and scientific research needs. In order to realize the burst mode operation, the subsystems of the pulse power device need to work in a certain time sequence. Therefore, it is necessary to develop a burst multi pulse generation system, control the sub-systems of the pulse power device to work according to the requirements, and realize the adjustable burst pulse parameters.
In this paper, FPGA control chip is used as the control center of burst multi pulse generation system to receive the control command of upper computer to generate burst multi pulse signal. The system can output two channels of burst multi pulse signals, the number of burst pulse trains is adjustable from 1 to 5, the interval between burst pulses is adjustable from 1 to 200 s, the number of internal pulses in burst pulse train is adjustable from 1 to 5, the internal pulse frequency of burst pulse train is adjustable from 1 to 100 Hz, and the parameters such as pulse width of burst pulse train can be adjusted [4-6].
1. Overall structure of the system
The burst multi pulse generation system includes four parts: upper computer monitoring interface, serial communication circuit, FPGA control circuit and input / output isolation circuit. The overall structure of the system is shown in Figure 1. The upper computer monitoring interface is based on visual Basic (VB) software for visual programming, through the upper computer monitoring interface can complete the serial communication protocol settings, burst multi pulse signal parameter settings and system start / stop, system self-test and other state control; upper computer and FPGA control chip use RS232 serial communication protocol, serial communication circuit includes FPGA serial port (UART) module, MAX232 chip and upper computer In the three parts of serial port, MAX232 chip realizes level conversion, which solves the problem that the signal level of FPGA is inconsistent with RS232 standard; FPGA chip adopts Altera Cycloneiv series, FPGA control circuit includes clock circuit, power supply circuit, program download circuit, SDRAM and flash storage circuit, reset circuit, etc.; input / output isolation circuit includes: serial port receiving signal, serial port sending signal and pulse output signal. In order to enhance the anti-interference ability of the system, FPGA input / output signals are all implemented by optical fiber transmission.
Program design of FPGA central control system
FPGA uses hardware logic to realize the control function. It has the characteristics of low power consumption, high speed, high working frequency and high integration. It can complete extremely complex timing and combination logic. In this paper, the main functions of FPGA control circuit are: receiving the data sent by upper computer through UART module from serial port, buffering, analyzing and storing the received data, and outputting two burst multi pulse signals according to the control command. FPGA control program is written in Verilog HDL hardware description language and developed on Quartus II 11.0 software platform. The core contents include UART data receiving module, data storage module and burst multi pulse generating module. The block diagram of FPGA program structure is shown in Figure 2.
2.1 UART data receiving module
The UART data receiving module designed in this paper mainly includes baud rate generation module and data receiving control module. The function is to receive the serial data sent by the upper computer from the serial port.
2.1.1 baud rate generation module
In the field of electronic communication, baud rate is the modulation speed, which is a measure of symbol transmission rate. 1 B / s means one symbol per second. The function of baud rate generation module is to generate clock which is synchronized with baud rate of RS-232 serial communication. Its basic idea is to divide the input clock of the system to get the required baud rate. In this design, the input clock of FPGA is 50 MHz, and the baud rate is 9 600 B / s.
2.1.2 data receiving control module
The data receiving control module mainly realizes the serial to parallel conversion of serial data, and the converted serial data is output according to the given data frame format. UART data receiving protocol adopts the format of 1 bit start bit, 8 bit data bit, 1 bit stop bit and no parity bit. At 9 600 B / s baud rate, the UART data acquisition steps are as follows:
(1) Idle state, waiting for data start bit 0;
(2) According to the flag of the start bit, the start of UART sequence is judged;
(3) Serial receiving 8-bit data from low to high;
(4) Judge the end bit 1, and a frame of data is received.
2.2 data storage module
The data received by UART data receiving module is buffered and parsed, and stored in the corresponding data register according to the address. Register is used as a digital device for data storage. The parameters of 2-channel burst multi pulse signal include the number of burst pulses, the interval of burst pulses, the number of burst pulses, the pulse frequency of burst trains, the pulse width of a burst burst pulse train, and the pulse width of B burst pulse train, etc., and a total of 21 count registers are required.
2.3 burst multi pulse generation module
The burst multi pulse generation module outputs the burst pulse signal according to the set parameters. The pulse width and the number of pulses are realized by counting the data stored in the data register. In this paper, finite state machine is used to realize the control of burst multi pulse generator.
Design of monitoring interface of upper computer
The monitoring interface of upper computer is programmed by VB software. The communication protocol is set up by calling MSComm serial communication control, and the data communication with FPGA is realized. The operator preset 2-channel burst multi pulse signal parameters through the monitoring interface. After the input is completed, click the parameter download button, and then click the start operation button. FPGA starts the generation of burst multi pulse signal. The upper computer monitoring interface is shown in Figure 3.
4 experimental debugging
Through the monitoring interface of the host computer, the serial communication protocol is set to realize the serial data communication with FPGA control chip; then the parameters of burst multi pulse train are set, and the data is saved to the upper computer data file by clicking the data save button; the set data is sent to the FPGA control chip through the serial port by clicking the data download button; after clicking start operation, the system starts to burst pulse The output of the punch. In the debugging experiment, the number of burst pulses is set as 1, the number of pulses in the burst pulse train is 2, the pulse frequency of burst pulse train is 5 Hz, the pulse width of burst a is 180 ms, and the pulse width of burst B is 5 ms. the waveform of single burst multi pulse train is shown in Fig. 4. Set the number of burst pulses to 5, the number of pulses in the burst pulse train is 5, 4, 3, 2 and 1 respectively, the pulse frequency of the burst pulse train is 5 Hz, the pulse width of a burst pulse train is 180 ms, and the pulse width of B burst pulse train is 5 ms. The waveform of multiple burst multi pulse trains is shown in Fig. 5.
The burst multi pulse generation system based on FPGA can output 2-channel burst multi pulse signals, and the pulse parameters can be adjusted. The system uses FPGA internal control module to realize multi-channel pulse timing output and UART interface control, which simplifies the hardware circuit design; the host computer uses serial port communication with FPGA through the human-computer interface programmed by VB software to realize remote control. The system realizes remote control function, adopts modular design, and has strong expansibility. This design can also be applied to other sequential control circuits.
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