1. Introduction

The application of ∑ – Δ modulation in digital signal processing and communication system is attracting more and more attention, because the implementation of ∑ – Δ modulation mainly adopts digital technology, and the accuracy of analog terminal is not high. Sigma delta modulation is usually used to modulate analog signal to generate a digital signal. But in many cases, the input signal itself is a digital signal, so it is necessary to study the implementation of ∑ – Δ modulation of digital signal.

In this paper, the basic principle of digital sigma delta modulator is described and studied, and then the structure of digital sigma delta modulator is described and designed, and finally FPGA implementation, and finally summarized.

2. Principle of sigma delta modulator

The sigma delta modulator is a nonlinear system, which is composed of a filter, a one bit quantizer with feedback loop and a subtractor. The working frequency of the quantizer is much higher than that of the Nyquist sampling frequency. The schematic diagram of the whole system is shown in Fig. 1. The bit stream signal obtained by modulating the input signal can recover the signal very well.

The difference between the signal and the feedback signal is accumulated in an accumulator (filter) and quantified by a quantizer. Assuming that the noise introduced by the quantizer is e (n), the relationship between Y (n), input U (n) and noise e (n) can be easily obtained in Z domain

It can be seen from equation (2.0) that the transfer function STF of the first order sigma delta system to the input signal is

It produces a unit delay for the signal, while NTF for noise is

The noise transfer function has a zero point at the DC, so it has the property of first-order high pass filter. It can be seen that the noise is pushed to the higher frequency band, and the quantization noise is greatly weakened within the signal bandwidth.

The basic principle of digital sigma delta modulator and its design based on FPGA

3. Design of digital sigma delta modulator

Figure 2 shows the system block diagram of a first-order digital sigma delta modulator which modulates the input 8-bit signal.

In this first-order digital sigma delta modulator, the subtractor, adder and quantizer operate on 8-bit signals. Subtraction is the operation of two 8-bit signals, so it must be a nine bit subtraction. The subsequent adder and delay unit form an accumulator to accumulate the values obtained by the previous subtraction circuit. We estimate the input of the accumulator, because ∑ – Δ The characteristics of the modulator are that if the previous accumulation result of the accumulator is a positive signal, then the feedback back to the input end is a negative value, otherwise, the feedback back to the input end is a positive value. In this way, the accumulation result of the accumulator will always be in a limited range. Therefore, we can estimate that the number of digits of the accumulator may only need 9 bits. The simulation waveforms shown in Fig. 3 and Fig. 4 are the output ranges of subtracter and adder when the sigma delta modulator modulates the eight bit signal. The abscissa represents the input range and the ordinate represents the maximum output value under various input conditions. The simulation results confirm our conjecture.

As can be seen from Fig. 3 and Fig. 4, when modulating the 8-bit signal, the absolute value of the output of the subtractor and accumulator circuit will not exceed 256. The signals of the actual circuit are represented by the complement code, and the operation is also the complement operation. Therefore, the design only needs to design a 9-bit subtractor and a 9-bit accumulator to meet the needs of the system.

In this system design, the operands of each operation unit are complements, and the highest bit is the sign bit. So the quantizer is a simple selector. If the sign bit is positive, the sign bit is negative and the sign bit is negative. The converter in the feedback loop is a simple data selector. Considering that the feedback signal will be subtracted, the output is negative when + 1 and output is selected at – 1 In this way, the subtractor is directly designed as an adder, which can simplify the design.

4. FPGA implementation of sigma delta modulator

After analyzing the specific unit in Fig. 2, we can get a specific FPGA realizable structure diagram as shown in Fig. 5.

When such a digital first-order sigma delta modulator is implemented on FPGA, only two 9-bit adders, a latch, a simple quantizer and a data selector are needed. Moreover, the quantizer and the data selector are extremely simple, so only a small amount of logic resources are needed in FPGA implementation.. This paper adopts xc3s200-pq208 of Xilinx Spartan 3 series. The input signal is 8-bit wide binary data data_ In [7:0], clock signal is CLK, reset signal is reset, output signal is single bit signal data_ out[0:0]。

This design is described by Verilog HDL language, compiled and synthesized by xilinxise6. I, and Xilinx XST is used as the synthesis tool. The main integrable Verilog HDL description of the module is given below

//First order digital sigma delta modulator

module sdelta(data_ in,clk,reset,data_ out);

input [7:0] data_ In; / / input signal

input [0:0] clk,reset;

output [0:0] data_ Out; / / output signal

reg [0:0] data_ out;

Reg [8:0] sum1; / / subtractor output

Reg [8:0] sum2; / / accumulator output reg

reg [8:0] latch_ Out; / / output of latch

reg [7:0] choose_ Out; / / data selector output

always @(data_ in or choose_ out) sum1 = data_ in + choose_ out;

always @(sum1 or latch_ out) sum2 = sum1 + latch_ out;

always @(posedge clk or posedge reset)

begin

if(reset)

begin

data_ out 《= 1‘b0;

latch_ out 《= 9’b000000000;

choose_ out 《=8‘b00000000;

End

else

begin

latch_ out 《= sum2;

data_ out 《= latch_ out[8]? 0:1;

choose_ out《=latch_ out[8]? 8’b01111111:8‘b1000000;

End

End

endmodule

5. Conclusion

In this paper, we start from the principle of ∑ – Δ modulation, and gradually give the system design of the first-order digital ∑ – Δ modulator and the final realizable FPGA model. Sigma delta modulator can be easily used in various digital systems, such as single bit neural network weight adjustment, single bit operation unit signal generation, which can greatly reduce the complexity of the system structure, and large-scale reduce the connection between circuit units. In order to solve the problem of oversampling frequency, it will be widely used.

The author’s Innovation: sigma delta modulator is usually used for the conversion of analog-to-digital signal, but there is little research on converting multi bit data into single bit data. In this paper, a practical structure and implementation of digital sigma delta modulator are presented. Due to the necessary range estimation simulation of adder, the system resources are greatly reduced, which can be easily applied to various kinds of applications In the case of single bit digital signal processing which needs to ensure the accuracy.

Editor in charge: GT

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