New RISC-V regulations released to prevent fragmentation and improve designer efficiency

Recently, RISC-V International announced the approval of the first four specifications and extensions in 2022, including RISC-V Efficient Tracking (E-Trace), RISC-V Supervisory Binary Interface (SBI ), RISC-V Unified Extensible Firmware Interface (UEFI) specification, and RISC-V Zmmul pure multiplication extension. Among them, E-Trace will accelerate the design of large-scale chip systems based on RISC-V, which not […]

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Axiomise Axiomatizes RISC-V Processors Through Formal Verification

Although it is economically feasible to design new microprocessors due to open-source architectures, testing and verification remain major hurdles. With the emergence of open source processor architectures such as RISC-V, chip design has become more and more democratized, and more and more organizations dare to dabble in processor design, from embedded microcontrollers to high-end desktop […]

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The RISC-V architecture spreads good news in the field of data centers

Electronic Enthusiast Network (text/Wu Zipeng) Previously, “Queen of the Bull Market” Catherine Wood mentioned in her 2021 technology trend release that the Intel era will end, and ARM, RISC-V and GPU will become mainstream processors.In her prediction, the X86 architecture, which currently accounts for nearly 100% of the data center field, will decline in the […]

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What does the new specification approved for RISC-V mean?

On December 2, US time, the RISC-V International Foundation announced that its members had approved 15 new specifications, including more than 40 extensions under the RISC-V instruction set architecture, with emphasis on its vector, scalar encryption and Hypervisor Three rules. The RISC-V International Foundation stated that these specifications have created new opportunities for markets such […]

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RISC-V architecture handles exceptions in machine mode

Last time we talked about processor interrupts and exceptions, we just overlooked this function from high to low. Did not fall to the real point, not specific to the details. There is a problem in the last chapter. Let me correct it here. The narrow-sense interruption and the narrow-sense exception together constitute a generalized exception […]

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Open source RISC-V architecture changes the game for IoT processors

Open source software has been one of the biggest catalysts in the tech world over the past decade. Today, the power of open source, the freedom it brings, and the community it engenders is also gaining traction in the hardware world. For these reasons, RISC-V is gaining popularity. This is an introduction to RISC-V and […]

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Open computing using RISC-V and memory fabrics

Over the past few years, we have witnessed dramatic changes in the way data is generated, processed, and further exploited for additional value and intelligence, all influenced by the emergence of new computational models based on deep learning and neural network applications. This profound change begins in the data center, where deep learning techniques are […]

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