Introduction of several timing of Axi bus protocol

Due to the frequent occurrence of Axi protocol in zynq architecture and common interface IP cores, the explanation timing of Xilinx’s protocol manual is relatively scattered. Therefore, the author collects several timing of Axi protocol for convenient programming. 1》AXI_ Lite protocol: (1) Read address channel, including arvalid, araddr and arready signals; (2) Read data channel, […]

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Application of intelligent lighting control based on Dali bus

Dali is a kind of digital addressable interface bus protocol for lighting control, which defines the communication protocol between electronic ballast and controller. In modern lighting control, with the advantage of digital addressability, the main control circuit is separated from the control circuit, that is, when the main power supply circuit changes, the control circuit […]

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Detailed explanation of SPI bus protocol and sequence diagram

SPI is the abbreviation of the English serial peripheral interface, as the name suggests, is the serial peripheral interface. SPI is a high-speed, full duplex, synchronous communication bus, and occupies only four wires on the pin of the chip, which saves the pin of the chip, and saves space and provides convenience for the layout […]

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Adopting wishbone bus can effectively solve the problems of IP core portability and design reuse

Tsinghua University embedded microprocessor chip design is a national key 863 project, single chip multiprocessor design is an extension of the project. Single chip multiprocessor is an effective way to improve the performance of processor, which has the main characteristics of low coupling and coarse-grained parallelism. Tsinghua University has successfully developed a 32-bit microprocessor with […]

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Design of PXI trigger bus interface based on CPLD

LinkedIn introduction PXI is the abbreviation of PCI extension for instrumentation. It is a modular instrument structure based on PCI computer local bus for extending PCI bus to test instrument field. Compared with CPCI system, PXI defines eight trigger buses, which can realize the synchronization and communication between modules in the system. PXI trigger bus […]

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