Common communication methods of I2C bus

The I2C bus is a simple, bidirectional two-wire synchronous serial bus. The I2C communication protocol is widely used in the communication between multiple integrated circuits (ICs) in the system due to its few pins, simple hardware implementation, strong scalability, and no need for external transceiver devices such as USART and CAN communication protocols. .   […]

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IIC bus entry knowledge popularization

Introduction to IIC The IIC (Inter-Integrated Circuit) bus is a two-wire serial bus developed by NXP (formerly PHILIPS) for connecting microcontrollers and their peripherals. It is mostly used for master-slave communication between the master controller and slave devices. It is used in the occasion of small data volume, the transmission distance is short, and there […]

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How to add AXI VIP to Vivado project

  In this new blog post, let’s talk about how to add the AXI VIP to a Vivado project and simulate the AXI4-Lite interface. Then, we will explain the signals used for AXI4-Lite transaction in the simulated waveform window. Using AXI VIP as an AXI4-Lite Master Interface (Tutorial) Download Design Files (attached to this article) […]

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Create AXI Sniffer IP for use in Vivado IP Integrator Tutorial

 introduction In some cases, it is useful to analyze the transfer transactions that are taking place in an AXI interface by sniffing it. In this article, I will show you how to create a basic AXI4-Lite Sniffer IP to count the read and write transactions that are happening on a specific address. First, HDL (Verilog) […]

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In-depth understanding of IIC bus

1.IIC bus structure 2.IIC timing 3.IIC concept 1. Start condition (start condiTIon): To mark the official start of the transfer, the master device sets SCL high (both SDA and SCL are high when the bus is idle), and then pulls SDA low, so that all slave devices know that the transfer is about to start […]

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How the I2C bus provides an efficient serial link between ICs

It is not practical to use a parallel bus on a printed circuit board (PC board) for communication and control between integrated circuits. Even an 8-bit processor uses 16 lines for the data side alone, and even more for the address bus. This is even more of a problem if multiple ICs need to be […]

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Several timing introductions of AXI bus protocol

Because the AXI protocol often appears in the ZYNQ architecture and common interface IP cores, Xilinx’s protocol manual explains the timing is relatively scattered. Therefore, the author collects several timing sequences of the AXI protocol, which is convenient for programming. (1) AXI_LITE protocol: (1) Read address channel, including ARVALID, ARADDR, ARREADY signals; (2) Read data […]

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I2C bus features and operation instructions

I2C bus physical topology The I2C bus is very simple in physical connection, consisting of SDA (serial data line) and SCL (serial clock line) and pull-up resistors. The communication principle is to generate the signals required by the I2C bus protocol for data transmission by controlling the high and low level timing of the SCL […]

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FPGA-based I²C protocol related content

Guided reading I²C (Inter-Integrated Circuit), in fact, is the abbreviation of I²C Bus. It is an integrated circuit bus in Chinese. It is a serial communication bus that uses a multi-master-slave architecture. Developed for connecting low-speed peripherals. The correct pronunciation of I²C is “I-squared-C”, while “I-two-C” is another incorrect but widely used pronunciation. Since October […]

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