Author of this article: Ren Junru

1. One of the ten pits of operational amplifiers – rail to rail

After stepping on the pitfall that the output voltage of the op amp cannot reach the power rail, I chose a rail-to-rail op amp, haha, so that the op amp can finally output to the power rail. Behind the joy is a hidden pit waiting for me:

Take a look at one of my favorite companies’ descriptions of rail-to-rail op amp products: “High-speed (>50MHz) rail-to-rail op amps support operation at lower supply voltages, swing closer to supply rails, and wider dynamic range .”Do you see it:

“Operate with lower supply voltages, swing closer to the supply rails, and have wider dynamic range.”

“Swing closer to the supply rail”



Look at the manual for a rail-to-rail op amp:

The output voltage does not reach the 5V of the power supply, why?

The output stage of the op amp can be simplified to the following structural form:

Due to the on-resistance of the MOS tube, when the current flows, a voltage drop is caused. Therefore, when the load is larger, the on-voltage drop is greater, and the output voltage cannot reach the rail.

Therefore, the rail-to-rail op amp is not completely able to make the output reach the power supply value. When it is used, it also needs to look at the relationship between the load and temperature (affecting the on-resistance value) to determine how much voltage the output can reach.

2. The second of the ten pits of op amps – input bias current that cannot be ignored

A voltage divider circuit is designed, theoretically input 1V, output 2V, but after a test, there are always nearly 6,700 mV more. If this is a 12-bit 3V range ADC, it will consume more than 600 codes.

It turns out that due to the TVS leakage current and the tube input bias current at the forward and reverse input terminals of the op amp, there is an input bias current at the two input terminals (and since no one device is exactly the same as the other device, the two The input bias current is not the same); these two bias currents will form a bias voltage with the external resistor, and then output to the back end, forming an error. If you unfortunately choose an op amp based on a BJT design, it has a large input bias current, which will cause a large post-stage error. The op amp shown in the picture below is really “not only big, but reckless”.

It is assumed below that the input bias current is the same for both inputs.

For the positive input terminal, the bias voltage brought by Ib+ is almost equal to 0, while for the reverse input terminal, the bias voltage brought by Ib- is equal to 350mV (when calculating, assume that Vout is grounded, which is equivalent to R1/ /R2). Therefore, what is needed is to add a resistor to the positive input to compensate for the error caused by the negative input.

As mentioned above, the positive and negative input bias currents are not the same, compensation can only reduce the offset voltage, and the difference between the positive and negative input bias currents is also called the offset current. When performing high-precision or small-signal sampling, you can choose a low-offset current op amp, because adding a compensation resistor also substitutes a new noise source, which should be added with caution.

Bias current is one of the main errors of operational amplifiers. In the following pits, some error sources that affect the subsequent stages will be introduced.

3. The third of the ten pits of operational amplifiers – fast falling PSRR

When I was a rookie engineer, I never considered PSRR when designing op amps. After I heard about PSRR, every time I chose an op amp, I would choose an op amp with higher PSRR on the basis of cost control.

For example, the PSRR of this op amp reaches 160dB:

According to the calculation formula:

Even if the power supply voltage changes within the range of 4.5V-5.5V, the influence of the power supply on the output of the op amp is only 10nV.

Unfortunately, this indicator refers to the DC change of the power supply voltage, and does not include the AC change of the power supply voltage (such as ripple). In the case of AC, this indicator will be greatly deteriorated. What is mentioned in the Spec. is only the DC change, and the AC change is in the following diagrams. Generally, non-senior engineers treat the diagrams with a smooth flip.

If the op amp circuit uses a switching power supply, and the decoupling and filtering are not done well, the input accuracy of the subsequent stage will be greatly affected. Look at the AC PSRR of the same op amp.

For the ripple of 500kHz switching frequency, PSRR+ deteriorates to only 50dB, assuming that the ripple size is 100mV, then the deterioration of the impact on the subsequent stage will reach 0.3mV. For many small-signal acquisition applications, this error is unacceptable. Therefore, some application scenarios even do a low-pass filter at the input of the power supply of the op amp (please pay attention to the power consumption of the resistor and the thermal noise of the resistor).

4. The fourth of the ten pits of the op amp – the compensation capacitor added indiscriminately

An “old engineer” once told me that if a capacitor is added to the feedback circuit, the circuit will not oscillate. As soon as I saw such a lofty word “oscillation”, I was stunned on the spot. In the future, all circuits will be connected with a small capacitor, so that it will be professional.

Until one day, I want to amplify a signal of 100kHz (lucky, the frequency is not too high, otherwise the voltage feedback op amp will not be able to play), and add a capacitor according to experience, and then. . . The signal was never normal again. . . Because, with the addition of this capacitive feedback impedance, it becomes less than 200Ω for a 100kHz signal, resulting in a change in the amplification factor.

However, this is not the point, the question is: Is a compensation capacitor really needed?

First, there is a pole inside the op amp (think of it as an RC low pass), which causes a phase change, up to -90°:

If you add another pole, it will change the phase again, and the maximum can be increased to 90°:

In this way, the phase is -180°. What’s the problem? That’s “oscillation”. Look at the gain of the voltage negative feedback op amp:

When the loop gain Aβ at certain frequency points is equal to 1 and the phase is -180°, at this time, Vout/Vin will become infinite, and the circuit will become unstable. Therefore, when a zero point is added externally, the op amp will oscillate at certain frequency points, such as the distributed capacitance on the pin, as shown in the figure below:

At this time, we add a capacitor, which is equivalent to artificially introducing a zero point to pull up the phase that has been pulled down. However, this distributed capacitance is generally very small, so that the position where the loop gain Aβ is equal to 1 is very far away. At the frequency point, the op amp has long been unable to work normally. According to the manual, when the op amp itself is at 100k, the phase margin is quite high, exceeding 90°, and there is no need to add additional compensation capacitors.

Therefore, for the specific situation, we must analyze it in detail, and we cannot be led away by “old engineers”.

5. The fifth of the ten pits of op amps – the wronged common mode input range

I have encountered a problem before. After the front-stage op amp is amplified, the op amp follows it into the ADC. The signal into the ADC is 0.3V-1.5V. It seems to be a very simple circuit, but in the actual measurement later, this operational amplifier with a single power supply voltage of 5V, when some boards output about 1.5V, its output value does not completely follow the input value, but is lower than the ratio The 1.5V signal is fine to follow, but once it is close to it, it is wrong.

Of course, this issue was brought up to the meeting of the hardware group, and the result of the final discussion was: “There is a problem with this op amp, we need to find the manufacturer, but we are an xx company, and no one else cares about us, so let’s change it. An op amp from another company”. Unfortunately, we wronged an op amp and didn’t find the cause of the problem. Fortunately, we happened to pick a working op amp without fully understanding the principle.

Let’s take a look at an indicator of this op amp, the common mode input range of the op amp:

The common mode input range of the op amp is an interval of the input voltage of the op amp, which represents the range in which the op amp can work linearly, that is, the common mode value of the input voltage is within this range, and when the input voltage changes, the output voltage can be linear change.

For the follower circuit, due to the existence of negative feedback, it can basically be considered that the voltage at the positive input terminal and the voltage at the negative input terminal are the same value, and when this op amp is powered by 5V, its common-mode input range is -0.1V to 1.5V. Therefore, when the input voltage is around 1.5V, the op amp cannot follow linearly normally.

Why can’t it follow? Let’s take a look at a triode amplifier circuit, which is also one of the components of the op amp, for an example.

When the input Vb changes, Ie will change accordingly with Vb, thus causing a change in Vc, which is following. If Vb continues to increase until the calculated value of Vc=Vcc-Ie x Rc is negative, but in fact Ie x Rc cannot exceed Vcc, then the amplifying circuit reaches saturation or even reverses the current, resulting in a fixed or reduced output voltage. peak or reverse etc.

6. The sixth of the ten pits of op amps – non-negligible slew rate

To make a 1pps drive circuit, the rising edge is required to be ≤ 5ns. After the signal output by the FPGA is driven by the op amp, it is found that the rising edge does not meet the requirements. Why? Because an important indicator, the slew rate, was not taken into account. The slew rate refers to the average value of the time change rate of the output voltage of the closed-loop amplifier when the input is a step signal. That is, if an ideal step signal is input, the output will be a signal with a slope, and the climbing rate of this signal is the slew rate.

Take a look at the slew rate of this op amp:

It can’t meet the requirements at all, 5ns can only climb 20mV, so the rising edge can’t meet the design requirements at all. What should I do? A pulse enhancement circuit is added to the flying lead in the later stage.

Pulse enhancement circuits C4 and R4 are equivalent to a differential circuit C4 and RL (when C x RL is much smaller than the slew rate time) plus a DC resistor R4, making the signal edge on the load RL steeper. Analyze it:

a. Capacitor C4 and RL form a voltage divider circuit. According to the calculation formula in the figure below, the rate of change of the voltage on C4 is equal to the voltage value on RL.

b. Then assuming that the rate of change of the capacitor voltage is almost unchanged in the range of 0-τ, then the voltage on the load RL is also almost constant. Once the capacitor starts to charge (the voltage changes), the voltage of the load RL rises to the peak . Record it as waveform 1, as shown in the figure below.

c. Then it begins to fall after the capacitor is charged. In order to solve the problem of no voltage without a rate of change, a DC resistance R4 is added to maintain the waveform. It is a straight-through waveform, that is, the original waveform, which is recorded as waveform 2.

d. After combining the two waveforms, due to waveform 1, the rising edge of waveform 2 is greatly enhanced, thus improving the rising edge of the synthesized waveform.

7. The seventh of the ten pits of operational amplifiers – the feedback resistance of current feedback operational amplifiers

In order to expand the external drive capability, a follower circuit is generally added to the last stage, and the current feedback op amp-CFA is selected to increase the output bandwidth of the op amp. It’s so simple, but unfortunately you just can’t tune it out. Let’s look at the picture first. It’s so simple, but unfortunately you just can’t tune it out. Let’s look at the picture first.

What power rail, common mode input range, gain product bandwidth, load capability, slew rate. . . I’ve thought about it all, right?

Because CFA and VFA (Voltage Feedback Operational Amplifier) ​​are different. Basically, the teacher used VFA as an example and explanation for the operation amplifier learned in school. The figure below is a model of the CFA op amp:

The difference between it and VFA is that both input terminals are no longer disconnected, and the inverting input resistance ZB is a very small value, but it must not be regarded as zero; its open-loop gain Gout is no longer very large, but Approximately equal to 1; its transimpedance Z can be considered infinite.

Therefore, the circuit model of the follower circuit of CFA is as follows:

Solving for Aβ is equal to:

Its closed-loop gain is:

When there is no feedback resistor ZF, A is approximately equal to 1, ZF tends to 0, Aβ tends to infinity, and the gain tends to 0, which is completely different from the desired follower circuit, which is what is often said on the Internet “CFA does not If you add a feedback resistor, there will be no signal.” (I didn’t find this sentence, I forgot where I saw it, I can only look at the introduction of feedback resistors in the CFA manual)

So, add a feedback resistor and the circuit will work fine.

PS: There are skills in the above derivation and calculation, which can only be calculated and deduced from Aβ, because the premise of CFA calculation is that the inverting input resistance ZB is a very small value; its transimpedance Z can be considered infinite, so the limit is Find a single variable, if you find the limit according to the final expression, a function, three variables (ZF tends to 0, ZB tends to 0, Z tends to infinity), it is impossible to play, as shown in the figure below.

8. The eighth of the ten pits of operational amplifiers – the failed AD620

When I was in college, instrument amplifier was definitely a high-end term. In the era when three op amps and differential op amps were commonly used, instrument amplifiers were synonymous with ultra-high common-mode rejection ratio and high temperature stability. The result is obtained by subtracting the two voltage differences of the positive and negative phases. This is definitely a good thing for collecting EEG signals (Electroencephalogram (EEG) is a method of recording brain activity using electrophysiological indicators).

Since the EEG signal amplitude is very small, plus the pre-amplification, it is only about 1V, so there is no problem if it is tried and tested. Later, it was not normal to do an industrial site signal detection. Let’s look at the picture first:

Collect 4-20mA current, get 1V-5V voltage difference, amplify it by 2 times and enter the post-stage ADC. In order to prevent the power consumption of the resistors from being too high, the three resistors R128, R129, and R130 are connected in parallel to obtain a value, and the value of 250Ω is finally obtained.

Let’s analyze it. The positive input terminal is 2V-10V, which is in line with the device input range (VCC-1.4V), and the inverting input terminal is 1V-5V. I added negative electricity, which is even more in line; then look at the magnification factor of 2 times, Vmax= 10V is also in line with the device output range (VCC-1.4V); there are no problems with power supply, magnification, decoupling, etc. Here’s a schematic that doesn’t appear to have any errors, but in reality, it will fail at high input voltage values.

Look at the internal principle of the instrument amplifier, and you will understand (here is a material that you have in hand, not the internal principle of the AD620, in fact, the principle of the instrument amplifier is similar)

The positive-phase input voltage and negative-phase input voltage are reflected in the R2 inside the instrument amplifier, and the real output voltage is reflected by V1out and V2out. In other words, the final increased voltage value is divided into two equal parts, one by Provided by V1out, it will be higher than V1, and the other is provided by V2out, which will be lower than V2.

Looking at the schematic diagram again, at 20mA, Vin+ reaches 10V, Vin- is 5V, magnified by 2 times, and Vin+ needs to be amplified to 12.5V inside the instrument amplifier. This has exceeded the power supply voltage of the instrument amplifier, so it is absolutely impossible to work normally.

9. Nine of the ten pits of the op amp – the sampling time of the ADC is dragged down by the op amp

The ADC collects the signal, and when the signal is stable, it is very accurate; when the signal changes, the data is unstable. Of course, the ADC has a sampling time, and the software engineer also knows that he has sampled 10 times and only the last 5 times, but the data is still in an unstable state. Let the hardware look at the circuit, the hardware engineer said, of course there is no problem with the circuit, it is all deducted from others, why is there a problem with me?

First look at the ADC’s ​​indicators Tcycmin=500ns and Tacqmin=80ns. This is a SAR ADC with a speed of Mbps, which is quite fast. Therefore, it samples 10 times continuously, and the time it takes is only about 10μs.

The process from signal input to output of the op amp is not a process without delay, but a process with delay and oscillation. At the same time, the time of this process will increase due to the PCB design of the subsequent circuit. As shown below:

Look at the specifications of the op amp, when it reaches 0.01% at 4V, the time is 5.1μs, and the fluctuation error brought by this time is 0.4mV, and in the range of 4V, the 1LSB of a 16-bit ADC is 0.06mV. The error can consume 6 or 7 codewords. If the distributed capacitance and wiring resistance are added, this time will be further increased, which will increase the stabilization time of the later stage, resulting in an even larger error.

Later, the software engineer lowered the sampling rate and increased the acquisition time, and the problem was resolved.

10. Ten of the ten pits of operational amplifiers – the forgotten power consumption

I have made a board with very strict power consumption requirements. Therefore, after the design is completed, I drew the power tree and calculated the power consumption of each device. If there is no excess, then I cast the board, debug, and the power consumption exceeds the standard when it is powered on. .

After a later inspection, it was found that there was a problem in the calculation of the power consumption of the op amp. Five op amp circuits like the one in the figure below were used.

Since it is a DC drive, only the static power consumption of the operational amplifier itself is considered in the calculation, PD=15V x 4.2mA =63mW, considering the maximum static power consumption, the power consumption margin is more than enough.

In fact, an important power consumption point is ignored: the voltage difference between the power supply voltage of the operational amplifier 15V and the output voltage (1V-4.5V) is all consumed in the operational amplifier. Calculated according to the maximum voltage difference, a circuit consumes 140mW. This kind of power dissipation has never been considered before, so all of them are selectively ignored. When the demand for power consumption is tight, the problem is exposed.

In the later revision, low voltage was selected to supply power to the op amp, which reduced the power dissipation and met the specification requirements.

Reviewing editor: Tang Zihong

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