With regard to Power PCB layout, wiring and debugging, as employees in the electronics industry, they must have their own set of operating habits. Not to mention anything else, at the beginning of today, let’s talk about some of Mr. lorry’s conclusions and suggestions in tonight’s live class.
Mr. lorry stressed that power engineers must work closely with PCB layout engineers to cope with the extremely challenging power design. Recklessness is not the best way to solve things.
In the power supply design, the following points should be noted:
In the system design layout planning, the power circuit should be as close to the load circuit as possible
The cooling circuit should be as close to the power circuit as possible to reduce thermal resistance
Select the correct number of layers and copper thickness
On the plate with heat dissipation and convection, pay attention to the layout of large passive devices (inductance and capacitance)
Do not obstruct the air convection between the chip and the MOSFET
In the problems of board layer stacking and circuit board layout and routing, Mr. lorry mainly explains by comparing the advantages and disadvantages, which is easier to master.
Sheet stacking problem
Which layer stacking design is the best?
• impedance reference:
Usually, DC power supply or ground plane is selected as AC reference plane.
• a basic guideline:
In general, the reference plane of multi-layer PCB design should not be divided.
Circuit board layout and routing
Small signal routing has to be routed at the reference layer
Select the route that has the least impact on the impedance rather than across the route to reduce the impedance of the power reference layer
The copper laying of power devices shall be as wide and short as possible
Multiple vias are used for interlayer connection to reduce impedance
The connection between power element pad and copper foil shall not be connected with very thin wiring or cross connection
Minimize the impedance of the wiring
Copper thickness and width calculation
This part mainly involves the calculation formula. With an example, it is easier to understand!
• copper resistivity (ohm / cm): (copper resistivity)
• resistance of copper:
• examples:
• summary and recommendations:
0.5 oz copper thickness = 0.7mil = 17.78um
1.0 oz copper thickness = 1.4mil = 35.56um
2.0 oz copper thickness = 2.8mil = 71.12um
4.0 oz copper thickness = 5.6mil = 142.24um
For all power system designs, copper thickness of 2oz or even thicker is recommended
Buck circuit layout and routing
Find the circuit of continuous current and intermittent current
Special attention shall be paid to minimize the loop area flowing through the pulse current, and the switching point of DV / dt shall be separated from other lines
Boost circuit layout and routing
The area enclosed by the pulse current circuit on the output side shall be as small as possible
Routing precautions
• the most sensitive routing
Current sampling (sense + / -), error amplifier input pin (VFB), error amplifier output pin (ith or vcomp), SGND
-Sense + / – try to route lines in pairs or differential lines
The wiring space shall be as small as possible, the filter capacitor shall be close to the chip pin, and the filter resistance shall be close to the filter capacitor.
-Other sensitive signals shall be kept away from noisy routing
• sensitive routing
Remote output voltage detection input / output (VOS + / -, diffout) of operational amplifier, synchronous pulse input terminal (pllftr), synchronous pulse output terminal (clkout)
-Synchronous pulse output terminal (clkout) is a sensitive signal and a signal with high noise, which is separated from other small signal routing.
• routing with the highest noise
SW, TG, BOOST, BG
-Separate from other sensitive routes
-Avoid overlapping of SW copper laying and sensitive wiring on two adjacent layers
-SW and TG shall be routed as close as possible to the routing or differential line to reduce the impedance of the loop
• power part
-Placement of power devices
-Copper laying planning
-Find out the circuit with intermittent current
-The decoupling capacitor is close to the MOSFET
-High current wiring is short, wide and has many vias
• controller section
-The decoupling capacitor is close to the chip
-SGND and PGND are separated
-Current sampling circuit
-Sensitive routing and high noise routing shall be separated
-Drive signal routing
-Select the appropriate lineweight
Layout routing analysis example
