At present, developers of space-based electronic systems are facing increasing pressure. When the project schedule is becoming more and more tight and the budget is repeatedly reduced, they need to provide higher system performance. However, space-based systems have a set of unique and strict size, weight and power consumption (swal?) restrictions, which is undoubtedly a thorny problem for designers.

In order to get twice the result with half the effort, major companies have adopted commercial finished products (COTS) devices such as FPGA. In terms of swap limitations, cost and work efficiency, the inherent flexibility of reconfigurable FPGA provides great help to the developers of space-based systems.

One way to leverage existing engineering and budget resources is to create flexible payloads that can be deployed to multiple space missions. Seakr engineering company uses the reconfigurable Xilinx virtex FPGA to create a flexible high-performance computing platform as the core of various space-based systems. Using this reconfigurable juice computing (RCC) method, high performance objectives can be achieved within the swap, cost and time constraints of multiple space missions. The most striking examples include seakr’s onboard processor developed for Raytheon’s advanced response tactical effectiveness military imaging spectrometer (Artemis), programmable space transceiver, programmable space IP modem and Orion vision processor currently under development.

Application independent processor architecture

This new platform, called application independent processor (AIP), integrates a series of scalar processors and RCC in a flexible and scalable architecture, and can support open standards, as shown in Figure 1. Because the processor has a flexible I / O architecture, it can? Build various boards to create different configurations most suitable for application requirements, which is called special task function. AIP uses the unique functions of Xilinx’s SRAM based FPGA to allow on orbit reconfiguration, so as to obtain higher flexibility and swap advantages. Ail? It also supports various anti single event effect (see) radiation technologies to ensure reliable operation in different orbits.

Space based system based on reconfigurable virtex FPGA

The core of AIP System Architecture is a reconfigurable computer board, which includes three virtex-4 FPGAs, as shown in Figure 2. Seakr has investigated the currently available components, and the results show that virtex FPGA is the only device that can achieve the performance goal and meet the requirements of space flight characteristics. For the most demanding applications, Xilinx provides virtex-4qv space class equipment. These space level FPGAs adopt the same architecture as commercial level FPGAs, but are specially processed and screened to meet the requirements of class Q and class v.

Space based system based on reconfigurable virtex FPGA

Vihex-4 FPGA can act as a coprocessor to accelerate the progress of key processing intensive tasks by working in coordination with sequential processors. The architecture of triple FPGA board is highly flexible and can meet the unique needs of different tasks. For example, the use of three FPGAs in the anti see technology can meet the requirements of the technology for component level redundancy; Multiple devices share a large coprocessor and use ring bus to connect three FPGAs through LVDS interface to realize high-speed communication between devices. With the extended 6U shape, there are two connectors on the board for communication between boards: one for CompactPCI backplane and the other for high-speed serial network.

Each FPGA can directly access the dedicated high-speed memory on the RCC board and the connector that supports expansion and customization through the high-speed mezzanine card. Using this architecture, the functions of RCC board can be extended by using specific I / O, memory, analog circuit and even additional logic. The component mezzanine card of anti see radiation architecture in specific applications is connected with RCC board through three connectors, and each connector can provide 170 LVDS I / O.

By moving the functional modules of specific tasks to the mezzanine card, the same FPGA based processing card can be used in a variety of unique applications. The common architecture helps to reduce project risk, reduce cost and shorten time.

Anti radiation effect in FPGA

The configuration circuit based on SRAM is easy to flip when exposed to radiation, so the reconfigurable system based on FPGA flying in space needs special consideration to ensure its reliable operation in high radiation environment. First, consider the selection of components. In addition to the industrial and military temperature level options, Xilinx also provides V-level virtex-4 and Virtex-5 FPGAs. These FPGAs are specially processed to prevent locking caused by radiation and ensure the performance under the total dose radiation effect. These devices can also withstand the further tempering of neutron and proton I seven beams, and reliably predict the frequency of single event upset (SEU) and single event function interruption in a specific orbit. This data can guide the engineer to select the anti overturning scheme suitable for the application and track.

The anti flip function of reconfigurable FPGA generally requires a combination of hardware triple redundancy and configuration memory clearing. Hardware triple redundancy includes triple key circuits, which can ensure continuous operation even after the turnover caused by radiation of a component. In addition, it also adds a voting circuit, which compares the signals from three logic branches and rejects the invalid signal caused by reversal.

Designers can choose from a series of schemes to meet the requirements of system performance and availability. One method is to use redundant FPGA and a radiation resistant external voting circuit. Another method is device level anti radiation, that is, configure triple mission critical logic in an FPGA and use the associated voting circuit. Traditionally, engineers have implemented the three mode redundancy (TMR) design manually. Now, Xilinx provides a special design tool, which can automatically implement fMR in FPGA. When selecting the anti radiation scheme, it will be affected by some factors, such as the size of the target circuit, the radiation level in the selected track and the running time requirements of the circuit.

The basic concept of memory clearing is to rewrite the configuration memory more frequently than the cumulative number of flips. Designers can choose from a series of memory clearing methods to adapt to different flip frequency and running time requirements. The simplest way is to reload the complete bitstream into the configuration memory. This method has low overhead, but requires the circuit to remain inoperative for at least one configuration cycle. For applications with more stringent requirements on running time, higher turnover rate or both, a more advanced method can also be adopted. For example, make full use of the partial reconstruction function of virtex FPGA, including the circuit of detecting memory flip and then reconstructing only a selected subset of the memory array.

Application status of AIP

AIP architecture has been successfully applied to four different space missions. By combining FPGA based RCC board and flexible mezzanine card, engineers can quickly build various processing and communication systems and implement anti radiation schemes suitable for the unique requirements of each space mission.

The first real product using ALP is the advanced reactive tactical effectiveness military imaging spectrometer Artemis, which will operate on the tacsat-3 satellite planned to be launched in the second quarter of 2009. Artemis aims to provide battlefield scene awareness. It uses data collected by satellites to perform advanced image processing, and then transmits these images to soldiers on the scene through narrowband downlink. Engineers realized that RCC scheme was needed to meet the requirements of spacecraft for size, weight and power consumption: the size was 7.8 × eleven point four one × 10 inches; Weighing 18 pounds; The power consumption is 40W (hard limit is 50W).

In the Artemis system, two virtex-4 FPGAs are responsible for pre-processing functions such as sensor data acquisition and calibration. The embedded processing system based on micro blazetm soft processor core can coordinate memory access and processor adjustment, while the PowerPC single board computer is used to realize image generation and target prompt. Figure 1 shows the Artemis system architecture.

Since the image data path is not mission critical, configuring memory clearing provides Artemis with appropriate anti radiation functions. Designers can meet the availability requirements without adopting three logical or redundant devices. In addition, commercial grade FPGA can be used to build flash memory; Each bit stream is configured with an FPGA to process specific waveforms and frequencies. In this way, the system will be able to support multiple waveforms with a minimum number of hardware, as shown in Table 1.

Space based system based on reconfigurable virtex FPGA

The highly flexible RCC board brings many advantages to the early stage of initial system development. The delay between requesting and receiving a series of frequency slots may exceed one year. Using reconfigurable hardware, designers can start development before receiving these frequency slots, thus reducing the system cost. Two virtex-4 FPGAs share the image processing workload, while the third FPGA remains idle to minimize power consumption.

After the first application of AIP, the work efficiency is greatly improved and the one-time engineering cost is significantly reduced, so that each subsequent project can save about one year of development time.

RCC helps implement flexible transceivers

AIP’s second space mission application is the programmable satellite transceiver. PST system provides the function of frequency agile satellite communication on multiple radio wave segments. Seakr engineers finally concluded that even high-end PowerPC processors cannot meet the swap requirements (i.e. 3.86 × six point eight five × Provide the necessary lifting capacity in the range of 7 inches, 10 pounds and 10W receiving power consumption and 45W transmitting power consumption).

In order to meet the above requirements, designers use the in system reconfiguration function of VINEX FPGA. The system stores multiple configuration bit streams in spectrum allocation to achieve the required frequency. In addition, this function allows developers to modify the system to meet the requirements of subsequent tasks. Seakr is developing more waveforms for future deployment.

The essence of the PST mission is to simplify the radiation resistance requirements. The communication system maintains end-to-end control over the channel while allowing data errors: once the data is damaged, the system will retransmit the affected packets. This inherent fault tolerance means that configuring memory clearing provides a suitable anti SEU radiation function for the control path. In order to protect the intermediate processing results, three memories are set up on the mezzanine card.

In order to complete the system, the AIP board, RF module and power module need to be connected through an extended 6u-shaped bottom plate, which can withstand vibration and other pressures during transmission.

Internet in space

Packet networks in space are expected to provide the same flexibility and robustness as terrestrial networks. For a long time, reconfigurable FPGA has been the mainstream wired network equipment. Just like the advantages shown in the programmable satellite internet protocol modem, it can provide excellent performance, high flexibility and accelerate the design process for space-based applications. PSIM can extract Ethernet frames from standard satellite communication waveforms and facilitate IP routing on spacecraft. Using packet satellite communication, data independent of electron beam and waveform can be routed through virtual circuits. Compared with standard elbow satellite communication channel, packet network improves scalability and traffic, realizes decentralized multicast, and is flexible enough to provide excellent quality of service.

PSIM includes 12 video-4v FPGAs mounted on 4 RCC cards, 2 sequential processors and 1 analog switch card on a rugged backplane. FPGA is responsible for waveform processing, while the sequential processor provides Ethernet interface and packet switching function.

In terms of availability, the space mission requires a scheme with stronger radiation resistance than that used in Artemis or PST. Because error recovery takes a long time and reduces availability, it can not meet the target requirements. Therefore, the system must be able to provide uninterrupted end-to-end control. Seakr engineers implemented an anti radiation scheme that can not only correct errors in real time, but also provide uninterrupted service.

Triple FPGA logic is set up in three devices on each RCC board. The radiation resistant logic device on the mezzanine card acts as the main voting device. The memory clearing operation is performed in the background, which is completely transparent to network operation. In addition, the mezzanine card also provides a physical interface to the router.

The space mission using PSIM is scheduled to start in the second quarter of 2009.

High performance video for manned spaceflight

The latest application of AIP architecture is the visual processing unit (VPU) of Orion manned spacecraft. Vpu can provide a reconfigurable platform for image processing algorithms, which is conducive to pose estimation, optical navigation and compression / decompression. The system receives image data from various sensors such as star tracker, visual navigation sensor, space docking camera and scene awareness camera.

Processing such huge data requires a combination of sequential processor and FGPA based RCC card. Virtex-4 FPGA can implement video processing algorithms such as function recognition, graphics coverage, tiling and video compression. In addition, they also integrate the MicroBlaze soft processor core to coordinate the communication between the algorithm core and the processor. The purpose of single board computer based on Leon fault-tolerant processor is to coordinate the system, handle errors, configure and monitor RCC and control interconnection.

The mezzanine card provides sensor interface and implements LVDS link connected with all three FPGAs to maximize the flexibility of video stream selection and anti radiation scheme.

Because the tasks performed by Vpu are “subject to subjective limitations of monitoring”, seakr engineers chose virtex-4qv space level FPGA and implemented a more powerful anti radiation scheme. By using the TMR method in combination with configuring memory clearing, it is ensured that control path errors are corrected transparently.

In short, through virtex FPGA, seakr engineers have not only developed an application independent processor for space applications, but also demonstrated the high flexibility of the processor in many space missions. RCC plays a major role in satellite based image processing and communication, highly flexible radio communication, space-based network and human space flight navigation.

Space grade virtex FPGA is a cots component that can provide the required performance for demanding data processing and communication systems. Using these reconfigurable FPGAs, a highly flexible and scalable architecture can be established, so as to reduce the development cost and shorten the design cycle. In addition to supporting rapid development and flexible ground manufacturing, virtex FPGA also provides on orbit reconfiguration function, so as to obtain more significant swap advantages.

The new generation of V-level reconfigurable FPGA can provide higher logic capacity, higher hardened IP block integration, higher performance and lower power consumption, so it can obtain more advantages in size, weight and power consumption. Radiation resistant reconfigurable virtex FPGA eliminates redundant implementation at logic level or device level, which not only simplifies the work of designers, but also further expands the advantages of swap.

Author: Ian troxel of seakr engineering company, Greg Lara of Xilinx company

Source: application of electronic technology, issue 4, 2009

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