In the high-speed digital circuit, the power consumption of CPU often increases with the increase of the main frequency. If the PCB layout is improper, it may cause the CPU to work unstable, which I have encountered before. When the Marvell 88f6282 CPU is running at 2GHz, the memory test shows that the CPU often doesn’t work, and there is no regular time point when it doesn’t work. However, when the CPU runs at 1.6GHz, this phenomenon will not occur.
The analysis is as follows
Memory test is a way to verify whether CPU and DDR can work normally under heavy load. When the system runs at 1.6GHz, it is normal, which indicates that the physical connection between CPU and DDR is OK. When it is upgraded to 2GHz, it will not work. There are two reasons for this phenomenon: one is timing, especially set up time and hold Time is greater than margin. At 1.6GHz, because the frequency is relatively low, that is, the clock cycle is relatively long, the timing may meet the requirements of the CPU for accessing DDR. However, after upgrading to 2GHz, the clock cycle becomes shorter, which may lead to the timing not meeting the requirements, resulting in read-write errors when the CPU accesses DDR. In order to verify this idea, we test the timing of CPU accessing DDR at 2GHz, and the results show that the timing meets the requirements. Another possibility is that the power supply of CPU is insufficient. According to the datasheet of Marvell 88f6282, the current consumption of CPU at 2GHz is 700mA higher than that at 1.6GHz.
But when we opened our PCB, we found VCC_ The CPU provides the current path through the power layer of the third layer through the vias. It is found that the effective width of the current path is about 40mil. According to the empirical formula, the 40mil line width can be calculated by 1A current in the surface layer, which can not meet the power supply requirements of the CPU.
Top layer VCC_ CPU network
Power layer VCC_ CPU network
The simpler way is to start from VCC_ Take a Flywire from the CPU power supply to the capacitor at the CPU power supply pin. The final method is to change the layout to make VCC_ The minimum line width of CPU power layer is 80mil. After the revision, this problem does not appear again.