In the program, when delay is needed, there are usually two methods: 1. Loop statement implementation. This method is simple and easy to use, but it can not get an accurate delay time; 2. Timer timing, can achieve accurate delay.

Concept of interrupt

What is an interrupt: when the CPU is processing an event a, another event B that occurs requests the CPU to process (generates an interrupt), and then the CPU temporarily interrupts the currently executing task to process event B. after processing event B, the CPU returns to the previous interrupt location and continues to execute the original event a. this process is generally called interrupt.

Schematic diagram of interrupt flow

Single chip microcomputer timer interrupt principle and S3C2440 timer application method

The event that interrupts the CPU is called the interrupt source. The interrupt source sends an interrupt request to the CPU. The CPU temporarily interrupts the originally executed event a and turns to event B. After event B is processed, continue to return to the original interrupted place (this process is called interrupt return, and the original interrupted place is a breakpoint) and continue to execute the original event.

Interrupt priority

Single chip microcomputer timer interrupt principle and S3C2440 timer application method

Benefits of interruption

(1) : improves CPU efficiency

CPU is the command center of computer. There are two methods of communication between CPU and peripheral equipment (such as key, display, etc.), query and interrupt

1: Query: whether the peripheral I / O needs service or not, the CPU should query it in turn every other period of time. In this query method, the CPU needs to spend some time on the query service

2: Interrupt: when the peripheral device needs communication service, it actively tells the CPU to stop the current work to process the interrupt program, so as to improve the work efficiency of the CPU.

(2) : real time processing can be realized

Peripherals may send a request interrupt signal at any time, and the CPU will process the request in time to meet the needs of the real-time system

(3) : faults can be handled in time

During the operation of the computer system, faults will inevitably occur, eg: power interruption, memory error, abnormal operation of peripheral devices, etc. at this time, the interrupt system can send a request to the CPU of the interrupt source in order to solve the fault.

Use steps of timer

1. Turn on the total interrupt:


2. Set timer working mode:

Tmod register: timer / counter mode control register

M1 and M0 are the setting bits of timer working mode, and a total of 4 working modes can be set.

Mode 0 (m1m0 = 00): 13 bit timing / counter

Mode 1 (m1m0 = 01): 16 bit timing / counter / / mode 1 is usually adopted

Mode 2 (m1m0 = 10): 8-bit automatic reset timing / counter

Mode 3 (m1m0 = 11): t0 is divided into two independent 8 as timing / counter; T1 stops counting in this way

3. Timer filling initial value

Key points of filling initial value:

① Single chip microcomputer crystal oscillator frequency: 12M, oscillation period is 1 / 12us

② The standard 51 single chip microcomputer is 12t, that is, 12 clock cycles, 12 x 1 / 12 US = 1US, that is, add 1US once.

For example, set the timer in working mode 1 and the initial value is 10ms:

TMOD = 0x01;

TH0 = (65536 – 10000);// 10000 represents 10000 1US

TL0 = (65536 – 10000);

4. Turn on timer interrupt



5. Turn on the timer (start counting)

Tr0 = 1: turn on timer 0

Tr1 = 1: turn on timer 1

6. Write interrupt service function (ISR)

Note: the interrupt service function cannot have parameters and return values

Timer user program

Single chip microcomputer timer interrupt principle and S3C2440 timer application method

be careful:

1: Timer and interrupt belong to the internal resources of MCU. There is no chip on the development board. At the same time, once the timer initialization program overflows, it will automatically execute the timer interrupt subroutine without calling ourselves. These are directly controlled by the hardware.

2: The timer calculates the fixed pulse, and its timing time can be calculated. It plays a better role than the delay function and can improve the efficiency of the CPU, because the delay function needs to be executed by the CPU. During this period, the CPU cannot perform other functions, and the CPU will call it automatically when the timer is needed.

Timer usage of S3C2440

System clock

First, you should understand the clock system of S3C2440. The main clock source of MCU is mainly external crystal oscillator or external clock. At present, the most used is external crystal oscillator. The mini2440 development board uses a 12Mhz external crystal oscillator. If the CPU only works at 12Mhz frequency, the utilization efficiency of the development board is very low, and the working efficiency of all hardware that depends on the system clock is also very low. If you want to improve the working efficiency of the CPU, you need to carry out a series of processing on the input clock. The process is as follows:

The crystal oscillator frequency is doubled by PLL (phase locked loop). S3c2440 has two PLLs, upll and MPLL. Upll is dedicated to USB module and provides 48mhz. MPLL provides fclk, hclk and PCLK. Fclk is the main frequency clock, which is used for ARM920T core; Hclk is used for AHB bus devices, such as memory control, interrupt control, LCD control, DMA and USB main modules; PCLK is used for APB bus devices, such as watchdog of peripheral devices, IIS, I2C, PWM, MMC interface, ADC, UART, GPIO, RTC and SPI.

S3c2440 supports the selection of frequency division ratio among fclk, hclk and PCLK, which is determined by hdivn and pdivn in clkdivn register. Therefore, we only need to determine fclk, and we can determine hclk and PCLK by setting hdivn and pdivn.

The multiple relationship between fclk and input clock fin (i.e. the crystal oscillator frequency is multiplied by PLL) is set through mpllcon register (as shown in Figure 1). Mpllcon register contains three parameters: MDIV, PDIV and sdiv. The formula is as follows:

MPLL(FCLK) = (2*m*Fin) / (p*2^s)

Where: M = MDIV + 8, P = PDIV + 2, s = sdiv

Single chip microcomputer timer interrupt principle and S3C2440 timer application method

Figure 1 mpllcon register

To sum up, the clock generation process is: external clock source → get fclk through register mpllcon → get hclk and PCLK through register clkdivn.


S3c2440 has five 16 bit timers. Timers 0, 1, 2 and 3 have PWM function; Timer 4 has only one internal timing and is not associated with the output pin; At the same time, timer 0 has a dead Zeno generator for high current equipment.

The input clock frequency signal of the timer is related to the prescaler and divider. As shown in Figure 2.

Prescaler: timers 0 and 1 share an 8-bit prescaler, and timers 2, 3 and 4 share another 8-bit prescaler. The prescaler value is configured by tcfg0, and the value range is 0 ~ 255.

Frequency divider: at the same time, each timer has a clock frequency divider, so that five different frequency divider signals can be generated. The value of frequency divider is configured by tcfg1, and the value can only be 2, 4, 8, 16, or external tclkn.

Single chip microcomputer timer interrupt principle and S3C2440 timer application method

Fig. 2 timer input clock block diagram

The specific formula is:

Timer input clock frequency = PCLK ÷ (prescaler + 1) ÷ divider

For example, given that PCLK = 50MHz, we want the input clock frequency of a timer to be 25kHz, so we need to configure prescaler = 249 and divider = 8, and the time will pass 0.04ms (1 ÷ 25000) every time the counter decreases by 1 × 1000)。

Tconn is the timer control register, which controls the opening and closing of the timer.

The timing count buffer register TCNTBn is used to store the initial value of the timer. When the timer is started, the value in TCNTBn will be loaded into the decrement counter tcntn.

The timing comparison buffer register tcmpbn is used to store the comparison value of the timer. The value of tcmpbn will be loaded into the comparison register tcmpn to compare with the down counter.

The working principle is:

(1) Load the initial value and comparison value of the timer into registers TCNTBn and tcmpbn.

(2) Set the timer control register TCON to start the timer. At this time, the values in tcmpbn and TCNTBn are loaded into registers tcmpn and tcntn.

(3) The timer will decrease 1 count, that is, tcntn will decrease 1 count. When tcmpn = tcntn, the output of toutn pin is reversed.

In normal applications, the value of tcmpbn is used for PWM. When the values of the down counter and the comparison counter are equal, the level will flip, so as to change the duty cycle. If it is only used for timing interrupt, set tcmpbn to 0, and when the down counter reaches 0, the timer interrupt request notifies the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of the corresponding TCNTBn will be automatically loaded into the down counter to continue the next operation. However, if the timer stops, for example, clearing the timer enable bit of tconn during timer operation mode, the value of TCNTBn will not be reloaded into the counter.

The timer of S3C2440 has a double buffer function to ensure that the current timer operation does not need to be stopped when the reloaded value changes during the next timer operation. Therefore, the current timer operation can also be completed successfully with the new timer value setting. The value of the timer can be written to TCNTBn, and the current count value of the timer can be read from tcnton. The value read by TCNTBn does not indicate the current state of the counter, but the reload value during the next timer duration. When tcntn is 0, the automatic reload operation will copy TCNTBn to tcntn. However, if tcntn is 0 and the enable bit of automatic reload is 0, tcntn will no longer operate.

After configuring the timer, the next step is to configure the interrupt, such as setting the interrupt mode (IRQ or FIQ), corresponding the timer execution function to the timing interrupt entry address, etc., which will not be repeated here.

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