DDR signal simulation is divided into signal quality analysis and timing analysis, and their emphasis is different. Let’s take a look at the following. After the DDR3 wiring of a designer has finished winding the same length, let’s simulate the topology as shown in Figure 1

Signal quality and timing analysis of DDR signal simulation

Figure 1

From the topological structure, the design is a main control drag four DDR particles, using T-shaped structure. The design branch is very good at equal length, it seems that there is no problem, but the simulated waveform is as shown in Figure 2

Signal quality and timing analysis of DDR signal simulation

Figure 2

Although the waveform voltage has passed the threshold level, the margin is very small, and the waveform is uneven, which is obviously not ideal. We only simulate the quality of a single signal here. If crosstalk is taken into account, it is difficult to guarantee that the waveform will not go wrong. The author has simulated this topology before, but the waveform is not so bad. In order to verify, the author changed the Ibis of the driver chip and kept the topology unchanged. The result is as follows: Figure 3:

Signal quality and timing analysis of DDR signal simulation

Figure 3

The signal quality in Figure 3 is better than that in Figure 2, but the result is not ideal, and the overshoot is still large. In fact, here, the author uses different Ibis models to prove that the output waveforms of different master chips are different. Sometimes our layout personnel have such a question. When we change the layout, we just change a master chip. The layout of the PCB itself has not been changed, even the connection relationship of the chip pins has not changed, and the wiring on the board does not need to be changed. This idea is wrong. If the topology of the same board remains unchanged, we need to replace the master chip The quality of the number will also be affected. At this time, our topology must be reevaluated.

OK, what are the reasons for the poor signal quality in Figure 2 and figure 3? Experienced netizens may find that the above T-shaped structure is not terminated. Similarly, the author also found this problem. The result shows that the signal quality is improved after adding the termination resistance, as shown in Figure 4

Signal quality and timing analysis of DDR signal simulation

Figure 4

Let’s look at a DDR3 design case. A designer added a series resistor to the data signal. The topology is shown in Figure 5 below

Signal quality and timing analysis of DDR signal simulation

Figure 5

There is ODT function at the particle end of DDR3, and there are six kinds of resistance values to choose from

Signal quality and timing analysis of DDR signal simulation

Figure 6

The waveform in Figure 6 has a small margin when the ODT is turned on. DDR3 has the ODT function. Why add the series resistance? So I decided to remove the series resistance, simulation waveform as shown in Figure 7

Signal quality and timing analysis of DDR signal simulation

Figure 7

After removing the series resistance, the waveform margin is larger, and the rising edge is not so slow. Therefore, for DDR particles with ODT function, there is no need to add series resistance when wiring, which not only saves components, but also saves wiring space.

It seems that Si engineers are very important. The success of high-speed design depends on the efforts of Si engineers. Topology design is not once and for all, which driver chip is suitable for which topology needs simulation evaluation. Simulation is a process of continuous attempt and exploration, which helps us to find the best match between interconnection and devices.

Source: pcbbbs

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