This chapter mainly introduces the signals related to PCIe bus.
PCIe bus related signals are mainly divided into the following categories:
Auxiliary signal line
The auxiliary signals are provided on the connector to assist with certain system level funcTIonality or implementaTIon. These signals are not required by the PCI Express architecture. The opTIonal low speed signals are defined to use the +3.3V or +3.3Vaux supplies， as they are the lowest common voltage available.
1.1 perst# signal
This signal is a global reset signal, which is provided by the processor system (RC). The processor system needs to provide this reset signal for PCIe slots and PCIe devices. The PCIe device uses this signal to reset the internal logic. When the signal is valid, the PCIe device will reset. PCIe bus defines a variety of reset modes, among which the implementation of cold reset and warm reset is related to the signal.
In order to support hot plug, a 1000pf capacitor is connected between the pin and GND during schematic design, and can be reset during hot plug.
1.2 REFCLK + and REFCLK – signals
A processor system may contain many PCIe devices, which can be connected to the PCIe slot as an add in card or as a built-in module directly connected to the PCIe link provided by the processor system without passing through the PCIe slot. Both PCIe devices and PCIe slots have REFCLK + and REFCLK – signals, which are used by PCIe slots to synchronize with the processor system.
In a processor system, dedicated logic is usually used to provide REFCLK + and REFCLK – signals to PCIe slots. The 100MHz clock source is provided by the crystal oscillator, and multiple clock sources in the same phase are generated through a “one push many” differential clock driver, which are connected one by one with the PCIe slot.
The REFCLK + / – of PCIe uses the lphcsl level.
REFCLK in V3.0 is described as follows:
REFCLK in v4.0 is described as follows:
Common Refclk Rx architectures are characterized by the Tx and Rx sharing the same Refclk source. A single Refclk source drives both the Generator and the DUT. It is typical that SSC would be applied.
A data clocked Rx architecture is characterized by requiring the receiver’s CDR to track the enTIrety of the low frequency jitter， including SSC. Since the Tx and Rx do not share a common Refclk， the jitter transfer function includes only the Tx PLL transfer function plus the lowpass characteristics of the CDR.
The 8.0 GT/s PCI Express Base Specification does not explicitly define the requirements for a separate Refclk architecture. This is the identical position taken by the base specification for 2.5 GT/s and 5.0 GT/s.
When tolerancing a PCI Express Rx in a separate Refclk architecture， the generator and DUT are furnished with separate Refclks that each are within ±300 PPM of the nominal frequency of 100 MHz. SSC must be turned off for both Refclk sources. These limitations are required to guarantee proper operation of the buffering and flow control in the Rx.
The PCIe slot requires a reference clock with a frequency range of 100MHz ± 300ppm and a single end swing of 0 ~ 0.7V. The processor system needs to provide reference clock for each PCIe slot, MCH, ICH and switch. Moreover, in a processor system, the distance difference between the reference clock signal generated by the clock driver and each PCIe slot (MCH, ICH and Swiss) is required to be within 15 inches. Generally, the propagation speed of the signal is close to the speed of light, about 6 in / NS. Therefore, the maximum transmission delay time difference of REFCLK + and REFCLK – signals between different PCIe slots is about 2.5ns.
When the PCIe device is connected to the PCIe slot as an add in card, the REFCLK + and REFCLK – signals provided by the PCIe slot can be used directly, or an independent reference clock can be used, as long as the reference clock is within 100MHz ± 300ppm. The method used by the built-in PCIe device is similar to that used by the add in card when processing REFCLK + and REFCLK – signals, but the PCIe device can use a separate reference clock instead of REFCLK + and REFCLK – signals.
The link control register in the PCIe device configuration space contains a “common clock configuration” bit. When the bit is 1, it indicates that the device and the opposite device of the PCIe link use the “in-phase” reference clock; If it is 0, it indicates that the reference clock used by the device and the opposite device of the PCIe link is asynchronous.
In the PCIe device, the default value of “common clock configuration” bit is 0. At this time, the reference clock used by the PCIe device has no connection with the opposite end device, and the reference clock used by the devices at both ends of the PCIe link can be set asynchronously. This asynchronous clock setting method is particularly important for remote connections using PCIe links.
In a processor system, if PCIe link is used for interconnection between chassis and chassis, because the reference clock can be set asynchronously, only differential signal line is required for data transmission between chassis and chassis without reference clock, which greatly reduces the difficulty of connection.
1.3 wake# signal
When the PCIe device enters the sleep state and the main power supply has stopped power supply, the PCIe device uses this signal to submit a wake-up request to the processor system to enable the processor system to provide the main power VCC for the PCIe device again. In PCIe bus, wake # signal is optional, so the mechanism of waking up PCIe devices with wake # signal is also optional. It is worth noting that the hardware logic that generates this signal must be powered by the auxiliary power supply Vaux.
Wake # is an open drain signal. All PCIe devices of a processor can wire and transmit wake # signals to the power controller of the processor system. When a PCIe device needs to be awakened, the device first sets the wake # signal to be valid, and then after a period of delay, the processor system starts to provide the main power VCC for the device, and uses the perst # signal to reset the device. At this time, the wake # signal needs to be kept low all the time. When the main power VCC is powered on, the perst # signal will also be set as invalid and the reset will end, and the wake # signal will also be set as invalid to end the whole wake-up process.
PCIe devices can use wake # signal to realize wake-up function and beacon signal to realize wake-up function. Unlike wake # signals, beacon uses in band signals, i.e. differential signals D + and D – to realize the wake-up function. Beacon signal DC balance consists of a set of pulse signals generated by D + and d-signals. The minimum value of these pulse signal widths is 2ns and the maximum value is 16us. When the PCIe device is ready to exit the L2 state (which is a low-power state used by the PCIe device), the beacon signal can be used to submit a wake-up request.
1.4. Smclk and smdat signals
The smclk and smdat signals are related to the SMBus (system mangement bus) of X86 processors. SMBus was proposed by Intel in 1995. SMBus consists of smclk and smdat signals. SMBus originates from I2C bus, but there are some differences with I2C bus.
The maximum bus frequency of SMBus is 100kHz, while I2C bus can support bus frequencies of 400kHz and 2MHz. In addition, the slave device on the SMBus has a timeout function. When the slave device finds that the clock signal sent by the master device remains low for more than 35ms, it will trigger the timeout reset of the slave device. Under normal conditions, the minimum bus frequency used by the master device of SMBus is 10kHz to avoid timeout of the slave device during normal use.
In SMBus, this timeout mechanism can be used if the master device needs to reset the slave device. The I2C bus can only use hardware signals to realize this reset operation. In I2C bus, if there is an error in the slave device, it is impossible to reset the slave device only through the master device.
SMBus also supports the alert response mechanism. When an interrupt is generated by the slave device, it will not be cleared immediately until the master device sends a command to the 0b0001100 address.
1.5 JTAG signal
JTAG (Joint Test Action Group) is an international standard test protocol, which is compatible with IEEE 1149.1 and is mainly used for chip internal test. At present, most devices support JTAG test standard. JTAG signal consists of trst#, TCK, TDI, TDO and TMS signals. Trst # is the reset signal; TCK is clock signal; TDI and TDO correspond to data input and data output respectively; TMS signal is mode selection.
1.6. Prsnt1 # and prsnt2 # signals
Prsnt1 # and prsnt2 # signals are related to hot plug of PCIe devices. In the add in card based on PCIe bus, prsnt1 # and prsnt2 # signals are directly connected, while in the processor motherboard, prsnt1 # signal is grounded, and prsnt2 # signal is high through pull-up resistance.
When the add in card is not inserted, the prsnt2# signal of the processor motherboard is connected to high by the pull-up resistance. When the add in card is inserted, the prsnt2# signal of the motherboard will be connected with the prsnt1# signal through the add in card. At this time, the prsnt2# signal is low. The hot plug control logic of the processor motherboard will capture this “low level” and know that the add in card has been inserted, so as to trigger the system software to process accordingly.
The working mechanism of add in card pulling out is similar to that of inserting. When the add in card is connected to the processor motherboard, the prsnt2# signal of the processor motherboard is low. When the add in card is unplugged, the prsnt2# signal of the processor motherboard is high. The hot plug control logic of the processor motherboard will capture this “high level” and know that the add in card has been pulled out, so as to trigger the system software to handle it accordingly.
Different processor systems process the hot plug of PCIe devices differently. In an actual processor system, the implementation of hot plug devices is much more complex than the example in the figure above. It is worth noting that the add in card needs to use the “long and short pin” structure when realizing the hot plug function.
Prsnt1 # and prsnt2 # signals use half the length of the golden finger as other signals. Therefore, when the PCIe device is inserted into the slot, prsnt1 # and prsnt2 # signals can not fully contact the slot until other golden fingers fully contact the PCIe slot and after a period of delay; When the PCIe device is pulled out of the PCIe slot, the two signals are disconnected from the PCIe slot first, and then after a period of delay, other signals can be disconnected from the slot. The system software can use this delay to perform some hot plug processing.
2. Data signal
The PCIe link uses the “end-to-end data transmission mode”. TX (transmission logic) and Rx (reception logic) are contained in the transmitting end and receiving end. A data path (Lane) of the PCIe bus link is composed of two groups of differential signals, a total of four signal lines, TxN / TXP and rxn / RxP. X1 contains one lane and X2 contains two lanes.
3. Power supply
The power supply of PCIe interface includes + 12V, + 3.3V and + 3.3vaux. The power supply capability of each power supply will be described in detail in the later article “PCIe bus power management” of pcix series.
The above is the signal introduction of PCIe bus. Later, PCIe bus will be introduced in terms of power management, reset, AC coupling capacitance, hardware circuit design, etc.