Sifive, the largest risc-v architecture manufacturer, recently announced that its openfive Department has successfully adopted TSMC’s N5 process technology to stream the company’s first SOC, using 2.5D packaged hbm3 storage units with a bandwidth of 7.2gbps. In the semiconductor industry, streaming means that the chip design has been completed and will generally be put into commercial use within one year.

The SOC can be used in AI, data center, high-performance computing and other scenarios, and can be further customized by sifive customers to meet their needs. At the same time, the components of this SOC can be licensed and used in other N5 designs without any effort.

Sifive successfully adopted the first SOC of TSMC N5 process technology

In terms of specifications, the chip is based on the sifive e76 32-bit CPU core, which is designed for AI, microcontroller, edge computing and other scenarios that do not require full precision. It is reported that the SOC contains a 32-bit CPU core sifive e76, which can be used in AI, microcontroller, edge computing and other relatively simple applications that do not require full precision.

It uses the D2D (die to die) interface of openfive for 2.5D packaging and the high bandwidth memory (hbm3) IP subsystem of openfive. The subsystem includes a controller and PHY, supports data transmission rates up to 7.2 Gbps, and allows high-throughput memory to provide data for DSA accelerators in computing intensive applications (including HPC, AI, network and storage).

Openfive’s low-power, low latency and highly scalable D2D interface technology can expand computing performance by connecting multiple bare chips together using organic substrates or silicon intermediaries in 2.5D packages.

Editor in charge: PJ

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